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preliminary data sheet august 2000 orca ? series 4 field-programmable gate arrays programmable features n high-performance platform design. 0.13 m seven-level metal technology. internal performance of >250 mhz (four logic levels). i/o performance of >416 mhz for all user i/os. over 1.5 million usable system gates. meets multiple i/o interface standards. 1.5 v operation (30% less power than 1.8 v oper- ation) translates to greater performance. embedded block ram (ebr) for onboard stor- age and buffer needs. built-in system components including an internal system bus, eight plls, and microprocessor interface. n traditional i/o selections. lvttl and lvcmos (3.3 v, 2.5 v, and 1.8 v) i/os. per pin-selectable i/o clamping diodes provide 3.3 v pci compliance. individually programmable drive capability. 24 ma sink/12 ma source, 12 ma sink/6 ma source, or 6 ma sink/3 ma source. two slew rates supported (fast and slew-limited). fast-capture input latch and input flip-flop (ff)/ latch for reduced input setup time and zero hold time. fast open-drain drive capability. capability to register 3-state enable signal. off-chip clock drive capability. two-input function generator in output path. n new programmable high-speed i/o. single-ended: gtl, gtl+, pecl, sstl3/2 (class i & ii), hstl (class i, iii, iv), zero-bus turn-around ( zbt* ), and double data rate (ddr). double-ended: ldvs, bused-lvds, lvpecl. customer defined: ability to substitute arbitrary standard-cell i/o to meet fast moving standards. n new capability to (de)multiplex i/o signals. new ddr on both input and output at rates up to 311 mhz (622 mhz effective rate). used to implement emerging rapidio ? back- plane interface specification. new 2x and 4x downlink and uplink capability per i/o (i.e., 104 mhz internal to 416 mhz i/o). n enhanced twin-quad programmable function unit (pfu). eight 16-bit look-up tables (luts) per pfu. nine user registers per pfu, one following each lut and organized to allow two nibbles to act independently, plus one extra for arithmetic carry/borrow operations. * zbt is a trademark of integrated device technologies inc. ? rapidio is a trademark of motorola, inc. table 1. orca series 4available fpga logic ? the usable gate counts range from a logic-only gate count to a gate count assuming 20% of the pfus/slics being used as rams. the logic-only gate count includes each pfu/slic (counted as 108 gates/pfu), including 12 gates per lut/ff pair (eight per pfu), an d 12 gates per slic/ff pair (one per pfu). each of the four pio groups are counted as 16 gates (three ffs, fast-capture latch, ou tput logic, clk, and i/o buffers). pfus used as ram are counted at four gates per bit, with each pfu capable of implementing a 32x4 ram (or 512 gates) per pfu. embedded block ram (ebr) is counted as four gates per bit plus each block has an additional 25k gates. 7k gates are used for each pll and 50k gates for the embedded system bus and microprocessor interface logic. both the ebr and plls are conse r- vatively utilized in the gate count calculations. note: devices are not pinout compatible with orca series 2/3. device columns rows pfus user i/o luts ebr blocks ebr bits (k) usable ? gates (k) OR4E2 26 24 624 400 4992 8 74 260470 or4e4 36 36 1296 576 10368 12 111 400720 or4e6 46 44 2024 720 16,192 16 147 530970 or4e10 60 56 3360 928 26,880 20 184 7401350 or4e14 70 66 4620 1088 36,960 24 221 9301700
table of contents contents page figure page 2 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas programmable features .............................................1 system features ........................................................4 product description ....................................................6 architecture overview .............................................6 programmable logic cells .........................................7 programmable function unit ...................................8 look-up table operating modes ..........................11 supplemental logic and interconnect cell ............21 plc latches/flip-flops .........................................25 embedded block ram .............................................27 ebr features ........................................................27 routing resources ...................................................31 clock distribution network ....................................... 31 primary clock nets ................................................31 secondary clock and control nets .......................31 edge clock nets ....................................................31 programmable input/output cells ............................31 programmable i/o .................................................31 inputs .....................................................................34 special function blocks ...........................................38 microprocessor interface (mpi) ................................48 embedded system bus (esb) .................................49 phase-locked loops ................................................52 fpga states of operation ........................................55 initialization ............................................................55 configuration .........................................................56 start-up .................................................................56 reconfiguration .....................................................60 partial reconfiguration ..........................................60 other configuration options ..................................60 bit stream error checking .....................................62 fpga configuration modes ......................................62 master parallel mode ............................................63 master serial mode ...............................................64 asynchronous peripheral mode ............................65 microprocessor interface mode .............................66 slave serial mode .................................................70 slave parallel mode ..............................................70 daisy chaining ......................................................71 daisy chaining with boundary-scan .....................72 absolute maximum ratings ......................................72 recommended operating conditions ...................73 electrical characteristics ..........................................73 pin information .........................................................75 pin descriptions ....................................................75 package compatibility ...........................................78 package outline drawings .....................................128 352-pin pbga .....................................................128 432-pin ebga .....................................................129 680-pin pbgam ..................................................130 ordering information................................................131 figure 1. series 4 top-level diagram .......................7 figure 2. pfu ports ...................................................9 figure 3. simplified pfu diagram .............................10 figure 4. simplified f4 and f5 logic modes .............12 figure 5. simplified f6 logic modes .........................13 figure 6. mux 4 x 1...................................................13 figure 7. mux 8 x 1...................................................14 figure 8. softwired lut topology examples.............15 figure 9. ripple mode ...............................................16 figure 10. counter submode ....................................17 figure 11. multiplier submode...................................18 figure 12. memory mode ..........................................19 figure 13. memory mode expansion example128 x 8 ram .......................................21 figure 14. slic all modes diagram ..........................22 figure 15. buffer mode ..............................................23 figure 16. buffer-buffer-decoder mode ....................23 figure 17. buffer-decoder-buffer mode ....................24 figure 18. buffer-decoder-decoder mode ................24 figure 19. decoder mode..........................................25 figure 20. latch/ff set/reset configurations ..........26 figure 21. ebr read and write cycles with write through ................................................................29 figure 22. series 4 pio image from orca foundry 33 figure 23. orca high-speed i/o banks ..................36 figure 24. pio shift register.....................................38 figure 25. printed-circuit board with boundary-scan circuitry ................................................................39 figure 26. boundary-scan interface..........................40 figure 27. orca series boundary-scan circuitry functional diagram ..............................................43 figure 28. tap controller state transition diagram ..44 figure 29. boundary-scan cell .................................45 figure 30. instruction register scan timing diagram ................................................................46 figure 31. pll_vf external requirements...............53 figure 32. pll naming scheme ...............................54 figure 33. fpga states of operation........................55 figure 34. initialization/configuration/start-up waveforms............................................................57 figure 35. start-up waveforms .................................59 figure 36. serial configuration data format autoincrement mode ............................................60 figure 37. serial configuration data formatexplicit mode ....................................................................60 figure 38. master parallel configuration schematic .63 figure 39. master serial configuration schematic ....65 figure 40. asynchronous peripheral configuration ...66 figure 41. powerpc /mpi configuration schematic.............................................................67 figure 42. configuration through mpi ......................68 figure 43. readback through mpi............................69
lucent technologies inc. 3 preliminary data sheet august 2000 orca series 4 fpgas figure page table page table of contents (continued) figure 44. slave serial configuration schematic ...... 70 figure 45. slave parallel configuration schematic ............................................................ 71 figure 46. daisy-chain configuration schematic ............................................................ 72 table pag e ta b l e 1 . orca series 4available fpga logic ................................................................... 1 table 2. system performance .................................. 5 table 3. look-up table operating modes ............... 11 table 4. control input functionality ......................... 11 table 5. ripple mode equality comparator functions and outputs ......................................... 18 table 6. slic modes ............................................... 22 table 7. configuration ram controlled latch/ flip-flop operation .............................................. 25 ta b l e 8 . orca series 4available embedded block ram .......................................................... 27 table 9. ram signals ............................................... 28 table 10. fifo signals ............................................ 29 table 11. constant multiplier signals ...................... 30 table 12. 8x8 multiplier signals ............................... 30 table 13. cam signals ............................................. 30 table 14. series 4 programmable i/o standards............................................................. 32 table 15. pio options ............................................. 35 table 16. pio register control signals ................... 35 table 17. pio logic options..................................... 36 table 18. compatible mixed i/o standards .............. 36 table 19. lvds i/o specifications ............................ 37 table 20. lvds termination pin .............................. 37 table 21. dedicated temperature sensing .............. 39 table 22. boundary-scan instructions ..................... 40 table 23. series 4e boundary-scan vendor-id codes.................................................. 41 table 24. tap controller input/outputs .................... 43 table 25. readback options .................................... 46 table 26. mpc 860 to orca mpi interconnection .................................................... 48 table 27. embedded system bus/mpi registers..... 50 table 28. interrupt register space assignments ..... 50 table 29. status register space assignments ........ 51 table 30. command register space assignments ........................................................ 51 table 31. ppll specifications.................................. 52 table 32. dpll ds-1/e-1 specifications.................. 53 table 33. dedicated pin per package ...................... 53 table 34. sts-3/stm-1 dpll specifications .......... 54 table 35. phase-lock loops index .......................... 54 table 36a. configuration frame format and contents ....................................................... 61 table 36b. configuration frame format and contents for embedded block ram ............. 61 table 37. configuration frame size ......................... 62 table 38. configuration modes................................. 63 table 39. absolute maximum ratings ...................... 73 table 40. recommended operating conditions....... 73 table 41. electrical characteristics .......................... 73 table 42. pin descriptions........................................ 75 table 43. orca i/os summary ............................... 78 table 44. or4e6 352-pin pbga pinout .................. 79 table 45. or4e6 432-pin ebga pinout .................. 92 table 46. or4e6 680-pin pbgam pinout ............. 106 table 47. series 4 package matrix ......................... 131 table 48. package options..................................... 131
4 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas programmable features (continued) new register control in each pfu has two inde- pendent programmable clocks, clock enables, local set/reset, and data selects. new lut structure allows flexible combinations of lut4, lut5, new lut6, 4-to-1 mux, new 8-to-1 mux, and ripple mode arithmetic functions in the same pfu. 32 x 4 ram per pfu, configurable as single- or dual-port. create large, fast ram/rom blocks (128 x 8 in only eight pfus) using the supplemen- tal logic and interconnect cell (slic) decoders as bank drivers. softwired luts (swl) allow fast cascading of up to three levels of lut logic in a single pfu through fast internal routing which reduces routing congestion and improves speed. flexible fast access to pfu inputs from routing. fast-carry logic and routing to all four adjacent pfus for nibble-, byte-wide, or longer arithmetic functions, with the option to register the pfu carry-out. n abundant high-speed buffered and nonbuffered rout- ing resources provide 2x average speed improve- ments over previous architectures. n hierarchical routing optimized for both local and glo- bal routing with dedicated routing resources. this results in faster routing times with predictable and efficient performance. n slic provides eight 3-statable buffers, up to 10-bit decoder, and pa l 1 -like and-or-invert (aoi) in each programmable logic cell. n new 200 mhz embedded quad-port ram blocks, two read ports, two write ports, and two sets of byte lane enables. each embedded ram block can be config- ured as: one-512 x 18 (quad-port, two read/two write) with optional built in arbitration. one-256 x 36 (dual-port, one read/one write). one-1k x 9 (dual-port, one read/one write). two-512 x 9 (dual-port, one read/one write for each). two rams with arbitrary number of words whose sum is 512 or less by 18 (dual-port, one read/one write). supports joining of ram blocks. two 16 x 8-bit content addressable memory (cam) support. fifo 512 x 18, 256 x 36, 1k x 9 or dual 512 x 9. constant multiply (8 x 16 or 16 x 8). dual-variable multiply (8 x 8). n built-in testability. full boundary-scan ( ieee 2 1149.1 and draft 1149.2 joint test access group (jtag)). programming and readback through boundary- scan port compliant to ieee draft 1532:d1.7. ts_all testability function to 3-state all i/o pins. new temperature-sensing diode used to deter- mine device junction temperature. system features n pci local bus compliant. n improved powerpc 3 860 and powerpc ii high-speed (66 mhz) synchronous mpi interface can be used for configuration, readback, device control, and device status, as well as for a general-purpose interface to the fpga logic, rams, and embedded standard-cell blocks. glueless interface to synchronous powerpc processors with user-configurable address space provided. n new embedded amba 4 specification 2.0 ahb sys- tem bus ( arm 4 processor) facilitates communication among the microprocessor interface, configuration logic, ebr, fpga logic, and embedded standard-cell blocks. embedded 32-bit internal system bus plus 4-bit parity interconnects fpga logic, microproces- sor interface (mpi), embedded ram blocks, and embedded standard-cell blocks with 100 mhz bus performance. included are built-in system registers that act as the control and status center for the device. n new network phase-locked loops (plls) meet itu-t g.811 specifications and provide clock conditioning for ds-1/e-1 and sts-3/stm-1 applications. n flexible general-purpose programmable plls offer clock multiply (up to 8x), divide (down to 1/8x), phase shift, delay compensation, and duty cycle adjustment combined. improved built-in clock management with programmable phase-locked loops (pplls) provide optimum clock modification and conditioning for phase, frequency, and duty cycle from 20 mhz up to 420 mhz. each ppll provides two separate clock outputs. n variable size bused readback of configuration data capability with the built-in mpi and system bus. n internal, 3-state, bidirectional buses with simple con- trol provided by the slic. 1. pal is a trademark of advanced micro devices, inc. 2. ieee a is registered trademark of the institute of electrical and electronics engineers, inc. 3. powerpc is a registered trademark of international business machines, inc. 4. amba and arm are trademarks of arm limited.
lucent technologies inc. 5 preliminary data sheet august 2000 orca series 4 fpgas system features (continued) n meets universal test and operations phy interface for atm (utopia) levels 1, 2, and 3. also meets proposed specifications for utopia level 4 for 10 gbits/s interfaces. n new clock routing structures for global and local clocking significantly increases speed and reduces skew (<200 ps for or4e4). n new local clock routing structures allow creation of localized clock trees anywhere on the device. n new ddr, qdr, and zbt memory interfaces support the latest high-speed memory interfaces. n new 2x/4x uplink and downlink i/o shift registers capabilities interface high-speed external i/os to reduced inter- nal logic speed. n orca foundry 2000 development system software. supported by industry-standard cae tools for design entry, synthesis, simulation, and timing analysis. table 2. system performance 1. implemented using 8 x 1 multiplier mode (unpipelined), register-to-register, two 8-bit inputs, one 16-bit output. 2. implemented using two 32 x 4 rams and one 12-bit adder, one 8-bit input, one fixed operand, one 16-bit output. 3. implemented using 8 x 1 multiplier mode (fully pipelined), two 8-bit inputs, one 16-bit output (seven of 15 pfus contain only pipelining registers). 4. implemented using 32 x 4 ram mode with read data on 3-state buffer to bidirectional read/write bus. 5. implemented using 32 x 4 dual-port ram mode. 6. implemented in one partially occupied slic, with decoded output setup to ce in the same plc. 7. implemented in five partially occupied slics. function no. pfus C2 unit 16-bit loadable up/down counter 2 282 mhz 16-bit accumulator 2 282 mhz 8 x 8 parallel multiplier multiplier mode, unpipelined 1 11.5 72 mhz rom mode, unpipelined 2 8175mhz multiplier mode, pipelined 3 15 197 mhz 32 x 16 ram (synchronous) single port, 3-state bus 4 4264mhz dual-port 5 4340mhz 128 x 8 ram (synchronous) single port, 3-state bus 4 8264mhz dual-port, 3-state bus 5 8264mhz address decode 8-bit internal, lut-based 0.25 1.37 ns 8-bit internal, slic-based 6 00.73 ns 32-bit internal, lut-based 2 4.68 ns 32-bit internal, slic-based 7 02.08 ns 36-bit parity check (internal) 2 4.68 ns
6 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas product description architecture overview the orca series 4 architecture is a new generation of sram-based programmable devices from lucent technologies microelectronics group. it includes enhancements and innovations geared toward todays high-speed systems on a single chip. designed with networking applications in mind, the series 4 family incorporates system-level features that can further reduce logic requirements and increase system speed. orca series 4 devices contain many new patented enhancements and are offered in a variety of packages and speed grades. the hierarchical architecture of the logic, clocks, rout- ing, ram and system-level blocks create a seamless merge of fpga and asic designs. modular hardware and software technologies enable system-on-chip inte- gration with true plug and play design implementation. the architecture consists of four basic elements: pro- grammable logic cells (plcs), programmable input/out- put cells (pios), embedded block rams (ebrs), and system-level features. these elements are intercon- nected with a rich routing fabric of both global and local wires. an array of plcs and its associated resources are surrounded by common interface blocks (cibs) which provide an abundant interface to the adjacent pios or system blocks. routing congestion around these critical blocks is eliminated by the use of the same routing fabric implemented within the program- mable logic core. pics provide the logical interface to the pios which provide the boundary interface off and onto the device. also, the interquad routing blocks (hiq, viq) separate the quadrants of the plc array and pro- vide the global routing and clocking elements. each plc contains a pfu, slic, local routing resources, and configuration ram. most of the fpga logic is per- formed in the pfu, but decoders, pa l -like functions, and 3-state buffering can be performed in the slic. the pios provide device inputs and outputs and can be used to register signals and to perform input demul- tiplexing, output multiplexing, uplink and downlink func- tions, and other functions on two output signals. the series 4 architecture integrates macrocell blocks of memory known as ebr. the blocks run horizontally across the plc array and provide flexible memory functionality. large blocks of 512x18 quad-port ram complement the existing distributed pfu memory. the ram blocks can be used to implement ram, rom, fifo, multiplier, and cam. system-level functions such as a microprocessor inter- face, plls, embedded system bus elements (located in the corners of the array), the routing resources, and configuration ram are also integrated elements of the architecture.
preliminary data sheet august 2000 lucent technologies inc. 7 orca series 4 fpgas product description (continued) 5-7536 (f)a figure 1. series 4 top-level diagram embedded system bus pic plc microprocessor interface (mpi) pfu slic fpga/system bus interface plls embedded block ram high-speed i/os clock pins pio programmable logic cells the plcs are arranged in an array of rows and col- umns. the location of a plc is indicated by its row and column so that a plc in the second row and the third column is r2c3. the array of actual plcs for every device begins with r3c2 in all series 4 generic fpgas. the plc consists of a pfu, slic, and routing resources. each pfu within a plc contains eight 4-input (16-bit) luts, eight latches/ffs, and one addi- tional ff that may be used independently or with arith- metic functions. the pfu is the main logic element of the plc, containing elements for both combinatorial and sequential logic. combinatorial logic is done in luts located in the pfu. the pfu can be used in dif- ferent modes to meet different logic requirements. the luts twin-quad architecture provides a configurable medium-/large-grain architecture that can be used to implement from one to eight independent combinatorial logic functions or a large number of complex logic func- tions using multiple luts. the flexibility of the lut to handle wide input functions, as well as multiple smaller input functions, maximizes the gate count per pfu while increasing system speed.
8 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas programmable logic cells (continued) the pfu is organized in a twin-quad fashion: two sets of four luts and ffs that can be controlled indepen- dently. each pfu has two independent programmable clocks, clock enables, local set/reset, and data selects with one available per set of quad ffs. luts may also be combined for use in arithmetic func- tions using fast-carry chain logic in either 4-bit or 8-bit modes. the carry-out of either mode may be registered in the ninth ff for pipelining. each pfu may also be configured as a synchronous 32 x 4 single- or dual-port ram or rom. the ffs (or latches) may obtain input from lut outputs or directly from invertible pfu inputs, or they can be tied high or tied low. the ffs also have programmable clock polarity, clock enables, and local set/reset. the luts can be programmed to operate in one of three modes: combinatorial, ripple, or memory. in com- binatorial mode, the luts can realize any 4-, 5-, or 6-input logic function and many multilevel logic func- tions using orca s swl connections. in ripple mode, the high-speed carry logic is used for arithmetic func- tions, comparator functions, or enhanced data path functions. in memory mode, the luts can be used as a 32 x 4 synchronous ram or rom, in either single- or dual-port mode. the slic is connected from plc routing resources and from the outputs of the pfu. it contains eight 3-state, bidirectional buffers and logic to perform up to a 10-bit and function for decoding, or an and-or with optional invert to perform pa l -like functions. the 3-state drivers in the slic and their direct connections from the pfu outputs make fast, true 3-state buses possible within the fpga. programmable function unit the pfus are used for logic. each pfu has 53 exter- nal inputs and 20 outputs and can operate in several modes. the functionality of the inputs and outputs depends on the operating mode. the pfu uses 36 data input lines for the luts, eight data input lines for the latches/ffs, eight control inputs (clk[1:0], ce[1:0], lsr[1:0], sel[1:0]), and a carry input (cin) for fast arithmetic functions and general- purpose data input for the ninth ff. there are eight combinatorial data outputs (one from each lut), eight latched/registered outputs (one from each latch/ff), a carry-out (cout), and a registered carry-out (reg- cout) that comes from the ninth ff. the carry-out sig- nals are used principally for fast arithmetic functions. there are also two dedicated f6 mode outputs which are for the 6-input lut function and 8-to-1 mux. figure 2 and figure 3 show high-level and detailed views of the ports in the pfu, respectively. the eight sets of lut inputs are labeled as k0 through k7 with each of the four inputs to each lut having a suffix of _x, where x is a number from 0 to 3. there are four f5 inputs labeled a through d. these are used for additional lut inputs for 5- and 6-input luts or as a selector for multiplexing two 4-input luts. four adjacent lut4s can also be multiplexed together with a 4-to-1 mux to create a 6-input lut. the eight direct data inputs to the latches/ffs are labeled as din[7:0]. registered lut outputs are shown as q[7:0], and combinatorial lut outputs are labeled as f[7:0]. the pfu implements combinatorial logic in the luts and sequential logic in the latches/ffs. the luts are static random access memory (sram) and can be used for read/write or rom. each latch/ff can accept data from its associated lut. alternatively, the latches/ffs can accept direct data from din[7:0], eliminating the lut delay if no combina- torial function is needed. additionally, the cin input can be used as a direct data source for the ninth ff. the lut outputs can bypass the latches/ffs, which reduces the delay out of the pfu. it is possible to use the luts and latches/ffs more or less independently, allowing, for instance, a comparator function in the luts simultaneously with a shift register in the ffs.
lucent technologies inc. 9 preliminary data sheet august 2000 orca series 4 fpgas programmable logic cells (continued) 5-5752(f)a figure 2. pfu ports the pfu can be configured to operate in four modes: logic mode, half-logic mode, ripple mode, and memory (ram/ rom) mode. in addition, ripple mode has four submodes and ram mode can be used in either a single- or dual- port memory fashion. these submodes of operation are discussed in the following sections. f5d k7_0 k7_1 k7_2 k7_3 k6_0 k6_1 k6_2 k6_3 k5_0 k5_1 k5_2 k5_3 k4_0 k4_1 k4_2 k4_3 f5c din7 din6 din5 din4 din3 din2 din1 din0 cin f5b k3_0 k3_1 k3_2 k3_3 k2_0 k2_1 k2_2 k2_3 k1_0 k1_1 k1_2 k1_3 k0_0 k0_1 k0_2 k0_3 f5a programmable function unit (pfu) q7 q6 q5 q4 q3 q2 q1 q0 cout regcout f7 f6 f5 f4 f3 f2 f1 f0 sel[0:1] ce[0:1] clk[0:1] lsr[0:1] lut603 lut647
10 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas programmable logic cells (continued) 5-9714(f) note: all multiplexers without select inputs are configuration selector multiplexers. figure 3. simplified pfu diagram k3_0mux k7_0mux d0 d1 sd sp ck lsr reg7 reset set q7 f7 0 din7 din7mux d0 d1 sd sp ck lsr reg6 reset set q6 f6 0 din6 din6mux d0 d1 sd sp ck lsr reg5 reset set q5 f5 0 din5 din5mux d0 d1 sd sp ck lsr reg4 reset set q4 f4 0 din4 din4mux lut647 0 a b c d a b c d a b c d a b c d fsdmux k7_2mux k6_0mux k6_2mux amux h7h6mux k7 k6 k5 k4 fscmux h5h4mux lut6mux f5d k7_0 k7_1 k7_2 k7_3 k6_0 k6_1 k6_2 k6_3 k5_0 k5_1 k5_2 k5_3 k4_0 k4_1 k4_2 f5c k4_3 d0 d1 sd sp ck lsr reg3 reset set q3 f3 0 din3 din3mux d0 d1 sd sp ck lsr reg2 reset set q2 f2 0 din2 din2mux d0 d1 sd sp ck lsr reg1 reset set q1 f1 0 din1 din1mux d0 d1 sd sp ck lsr reg0 reset set del0 del1 del2 q0 f0 0 din0 din0mux lut603 0 a b c d a b c d a b c d a b c d fsbmux k3_2mux k2_0mux k2_2mux bmux h3h2mux k3 k2 k1 k0 f5amux h1h0mux lut6mux f5b k3_0 k3_1 k3_2 k3_3 k2_0 k2_1 k2_2 k2_3 k1_0 k1_1 k1_2 k1_3 k0_0 k0_1 k0_2 f5a k0_3 0 clk1 clk1mux 0 sel1 sel1mux 1 ce1 ce1mux ce47mux 0 lsr1 lsr1mux lsr47mux 0 cin 1 0 0 clk0 clk0mux 0 sel0 sel0mux 1 ce0 ce0mux cebmux 0 lsr0 lsr0mux ce03mux 1 0 lsrbmux lsr03mux 1 0 d0 sp ck lsr reg8 reset set reccout cout sr1modeattr sr1mode ce1_over_lsr1 lsr1_over_ce1 rsync1 sr0modeattr sr0mode ce0_over_lsr0 lsr0_over_ce0 async0 regmode_top ff latch reg 4 through 7 this is always a flipflop regmode_bot ff latch reg 0 through 3 logic mlogic ripple ram rom enabled disabled gsr pfu modes cinmux 0 0 del3 del0 del1 del2 del3 del0 del1 del2 del3 del0 del1 del2 del3 del0 del1 del2 del3 del0 del1 del2 del3 del0 del1 del2 del3 del0 del1 del2 del3 del0 del1 del2 del3
lucent technologies inc. 11 preliminary data sheet august 2000 orca series 4 fpgas programmable logic cells (continued) look-up table operating modes the operating mode affects the functionality of the pfu input and output ports and internal pfu routing. for exam- ple, in some operating modes, the din[7:0] inputs are direct data inputs to the pfu latches/ffs. in memory mode, the same din[7:0] inputs are used as a 4-bit write data input bus and a 4-bit write address input bus into lut memory. table 3 lists the basic operating modes of the lut. figure 4figure 7 show block diagrams of the lut operating modes. the accompanying descriptions demonstrate each modes use for generating logic. table 3. look-up table operating modes pfu control inputs each pfu has eight routable control inputs and an active-low, asynchronous global set/reset (gsrn) signal that affects all latches and ffs in the device. the eight control inputs are clk[1:0], lsr[1:0], ce[1:0], and sel[1:0], and their functionality for each logic mode of the pfu is shown in table 4. the clock signal to the pfu is clk, ce stands for clock enable, which is its primary function. lsr is the local set/reset signal that can be configured as syn- chronous or asynchronous. the selection of set or reset is made for each latch/ff and is not a function of the signal itself. sel is used to dynamically select between direct pfu input and lut output data as the input to the latches/ffs. all of the control signals can be disabled and/or inverted via the configuration logic. a disabled clock enable indicates that the clock is always enabled. a disabled lsr indicates that the latch/ff never sets/resets (except from gsrn). a disabled sel input indicates that din[7:0] pfu inputs or the lut outputs are always input to the latches/ ffs. table 4. control input functionality mode function logic 4-, 5-, and 6-input luts; softwired luts; latches/ffs with direct input or lut input; cin as direct input to ninth ff or as pass through to cout. half logic/ half ripple upper four luts and latches/ffs in logic mode; lower four luts and latches/ffs in ripple mode; cin and ninth ff for logic or ripple functions. ripple all luts combined to perform ripple-through data functions. eight lut registers available for direct-in use or to register ripple output. ninth ff dedicated to ripple out, if used. the submodes of ripple mode are adder/subtractor, counter, multiplier, and comparator. memory all luts and latches/ffs used to create a 32x4 synchronous dual-port ram. can be used as single-port or as rom. mode clk[1:0] lsr[1:0] ce[1:0] sel[1:0] logic clk to all latches/ ffs lsr to all latches/ffs, enabled per nibble and for ninth ff ce to all latches/ffs, selectable per nibble and for ninth ff select between lut input and direct input for eight latches/ffs half logic/ half ripple clk to all latches/ ffs lsr to all latches/ff, enabled per nibble and for ninth ff ce to all latches/ffs, selectable per nibble and for ninth ff select between lut input and direct input for eight latches/ffs ripple clk to all latches/ ffs lsr to all latches/ffs, enabled per nibble and for ninth ff ce to all latches/ffs, selectable per nibble and for ninth ff select between lut input and direct input for eight latches/ffs memory (ram) clk to ram lsr0 port enable 2 ce1 ram write enable ce0 port enable 1 not used memory (rom) optional for synchronous outputs not used not used not used
12 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas programmable logic cells (continued) logic mode the pfu diagram of figure 3 represents the logic mode of operation. in logic mode, the eight luts are used individually or in flexible groups to implement user logic functions. the latches/ffs may be used in con- junction with the luts or separately with the direct pfu data inputs. there are three basic submodes of lut operation in pfu logic mode: f4 mode, f5 mode, and the f6 mode. combinations of the submodes are possible in each pfu. f4 mode, shown simplified in figure 4, illustrates the uses of the basic 4-input luts in the pfu. the output of an f4 lut can be passed out of the pfu, captured at the luts associated latch/ff, or multiplexed with the adjacent f4 lut output using one of the f5[a:d] inputs to the pfu (not shown). only adjacent lut pairs (k 0 and k 1 , k 2 and k 3 , k 4 and k 5 , k 6 and k 7 ) can be multi- plexed, and the output always goes to the even-num- bered output of the pair. the f5 submode of the lut operation, shown simpli- fied in figure 4, indicates the use of 5-input luts to implement logic. 5-input luts are created from two 4-input luts and a multiplexer. the f5 lut is the same as the multiplexing of two f4 luts described previously with the constraint that the inputs to both f4 luts be the same. the f5[a:d] input is then used as the fifth lut input. the equations for the two f4 luts will differ by the assumed value for the f5[a:d] input, one f4 lut assuming that the f5[a:d] input is zero, and the other assuming it is a one. the selection of the appropriate f4 lut output in the f5 mux by the f5[a:d] signal creates a 5-input lut. two 6-input luts are created by shorting together the inputs of four 4-input luts (k0:3 and k4:7) which are multiplexed together. the f5 inputs of the adjacent f4 luts derive the fifth and sixth inputs of the f6 mode as shown in figure 5. the f6 outputs, lut603 and lut647, are dedicated to the f6 mode or can be used as the outputs of mux8x1. mux8x1 modes as shown in figure 7 are created by programming adjacent 4-input luts to 2x1 muxs and multiplexing down to create mux8x1. other functions can be implemented from the configuration shown in figure 5 where the four lut4s drive the 4x1 mux in each half of the pfu if the lut4 inputs are not tied to the same inputs. both f6 mode and mux8x1 are available in the upper and lower pfu nibbles. any combination of f4 and f5 luts is allowed per pfu using the eight 16-bit luts. examples are eight f4 luts, four f5 luts, a combination of four f4 plus two f5 luts, a combination of two f4, one f5, plus one f6, or a combination of one f5, one mux21 of two lut4s, and one mux41 of four lut4s. 5-9733(f) figure 4. simplified f4 and f5 logic modes k7_0 k7_1 k7_2 f5d lut4 lut4 2x1 mux f6 k7_3 k6_0 k6_1 k6_2 k6_3 k5_0 k5_1 k5_2 f5c lut4 lut4 2x1 mux f4 k5_3 k4_0 k4_1 k4_2 k4_3 k3_0 k3_1 k3_2 f5b lut4 lut4 2x1 mux f2 k3_3 k2_0 k2_1 k2_2 k2_3 k1_0 k1_1 k1_2 f5a lut4 lut4 2x1 mux f0 k1_3 k0_0 k0_1 k0_2 k0_3 k7 f7 k6 f6 k5 f5 k4 f4 k3 f3 k2 f2 k1 f1 k0 f0
lucent technologies inc. 13 preliminary data sheet august 2000 orca series 4 fpgas programmable logic cells (continued) 5-9734(f)a figure 5. simplified f6 logic modes 5-9735(f) figure 6. mux 4x1 k7_0 k7_1 k7_2 k7_3 k6_0 k6_1 k6_2 k6_3 k5_0 k5_1 k5_2 k5_3 k4_0 k4_1 k4_2 k4_3 f5d f5c lut4 lut4 lut4 lut4 4x1 mux k3_0 k3_1 k3_2 k3_3 k2_0 k2_1 k2_2 k2_3 k1_0 k1_1 k1_2 k1_3 k0_0 k0_1 k0_2 k0_3 f5b f5a lut4 lut4 lut4 lut4 lut603 4x1 mux lut647 k7_0 k7_1 k7_2 f5d lut4 lut4 2x1 mux k6_0 k6_1 k6_2 f4 k5_0 k5_1 k5_2 f5c lut4 lut4 2x1 mux k4_0 k4_1 k4_2 f3 k3_0 k3_1 k3_2 f5b lut4 lut4 2x1 mux k2_0 k2_1 k2_2 f2 k1_0 k1_1 k1_2 f5a lut4 lut4 2x1 mux k0_0 k0_1 k0_2 f0
14 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas programmable logic cells (continued) 5-9736(f)a figure 7. mux 8x1 softwired lut capability uses f4, f5, and f6 luts, along with mux21 and mux41 blocks together with internal pfu feedback routing, to generate complex logic functions up to three lut-levels deep. multiplexers can be inde- pendently configured to route certain lut outputs to the input of other luts. in this manner, very complex logic functions, some of up to 22 inputs, can be implemented in a single pfu at greatly enhanced speeds. it is important to note that an lut output that is fed back for softwired use is still available to be registered or output from the pfu. this means, for instance, that a logic equation that is needed by itself and as a term in a larger equa- tion need only be generated once, and plc routing resources will not be required to use it in the larger equation. k7_0 k7_1 k7_2 f5d lut4 lut4 k6_0 k6_1 k6_2 lut4 lut4 k5_0 k5_1 k5_2 k4_0 k4_1 k4_2 f5c lut4 k3_0 k3_1 k3_2 f5b lut4 lut4 k2_0 k2_1 k2_2 lut4 lut4 k1_0 k1_1 k1_2 k0_0 k0_1 k0_2 f5a lut4 mux8x1 4x1 mux 4x1 mux [lut647] mux8x1 [lut603]
lucent technologies inc. 15 preliminary data sheet august 2000 orca series 4 fpgas programmable logic cells (continued) 5-5753 (f) 5-5754 (f) figure 8. softwired lut topology examples f4 f4 f4 f4 f4 f4 f4 f4 four 7-input functions in one pfu f5 f5 f5 f5 two 9-input functions in one pfu f5 f5 f5 f5 one 17-input function in one pfu f5 f5 f4 one 21-input function in one pfu f4 f4 f4 f4 f4 f4 f4 two 10-input functions in one pfu f4 f4 f4 f4 3 one of two 21-input functions in one pfu one 22-input function in one pfu f5 f6 f4 f4 f4 f4 f4 f5 4-input lut 5-input lut f6 6-input lut
16 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas programmable logic cells (continued) half-logic mode series 4 fpgas are based upon a twin-quad architec- ture in the pfus. the byte-wide nature (eight luts, eight latches/ffs) may just as easily be viewed as two nibbles (two sets of four luts, four latches/ffs). the two nibbles of the pfu are organized so that any nib- ble-wide feature (excluding some softwired lut topolo- gies) can be swapped with any other nibble-wide feature in another pfu. this provides for very flexible use of logic and for extremely flexible routing. the half- logic mode of the pfu takes advantage of the twin- quad architecture and allows half of a pfu, k [7:4] and associated latches/ffs, to be used in logic mode while the other half of the pfu, k [3:0] and associated latches/ffs, is used in ripple mode. in half-logic mode, the ninth ff may be used as a general-purpose ff or as a register in the ripple mode carry chain. ripple mode the pfu luts can be combined to do byte-wide ripple functions with high-speed carry logic. each lut has a dedicated carry-out net to route the carry to/from any adjacent lut. using the internal carry circuits, fast arithmetic, counter, and comparison functions can be implemented in one pfu. similarly, each pfu has carry-in (cin, fcin) and carry-out (cout, fcout) ports for fast-carry routing between adjacent pfus. the ripple mode is generally used in operations on two data buses. a single pfu can support an 8-bit ripple function. data buses of 4 bits and less can use the nibble-wide ripple chain that is available in half-logic mode. this nibble-wide ripple chain is also useful for longer ripple chains where the length modulo 8 is four or less. for example, a 12-bit adder (12 modulo 8 = 4) can be implemented in one pfu in ripple mode (8 bits) and one pfu in half-logic mode (4 bits), freeing half of a pfu for general logic mode functions. each lut has two operands and a ripple (generally carry) input, and provides a result and ripple (generally carry) output. a single bit is rippled from the previous lut and is used as input into the current lut. for lut k 0 , the ripple input is from the pfu cin or fcin port. the cin/fcin data can come from either the fast-carry routing (fcin) or the pfu input (cin), or it can be tied to logic 1 or logic 0. in the following discussions, the notations lut k 7 /k 3 and f[7:0]/f[3:0] are used to denote the lut that pro- vides the carry-out and the data outputs for full pfu ripple operation (k 7 , f[7:0]) and half-logic ripple operation (k 3 , f[3:0]), respectively. the ripple mode diagram (figure 9) shows full pfu ripple operation, with half-logic ripple connections shown as dashed lines. the result output and ripple output are calculated by using generate/propagate circuitry. in ripple mode, the two operands are input into k z [1] and k z [0] of each lut. the result bits, one per lut, are f[7:0]/f[3:0] (see figure 9). the ripple output from lut k 7 /k 3 can be routed on dedicated carry circuitry into any of four adja- cent plcs, and it can be placed on the pfu cout/ fcout outputs. this allows the plcs to be cascaded in the ripple mode so that nibble-wide ripple functions can be expanded easily to any length. result outputs and the carry-out may optionally be reg- istered within the pfu. the capability to register the ripple results, including the carry output, provides for improved counter performance and simplified pipelin- ing in arithmetic functions. 5-5755(f). figure 9. ripple mode f7 k 7 [1] k 7 [0] k7 dq c c dq q7 regou t cout f6 k 6 [1] k 6 [0] k6 dq q6 f4 k 4 [1] k 4 [0] k4 dq q4 f3 k 3 [1] k 3 [0] k3 dq q3 f2 k 2 [1] k 2 [0] k2 dq q2 f1 k 1 [1] k 1 [0] k1 dq q1 f5 k 5 [1] k 5 [0] k5 dq q5 f0 k 0 [1] k 0 [0] k0 dq q0 c in/fcin fcout
lucent technologies inc. 17 preliminary data sheet august 2000 orca series 4 fpgas programmable logic cells (continued) the ripple mode can be used in one of four submodes. the first of these is adder-subtractor submode . in this submode, each lut generates three separate out- puts. one of the three outputs selects whether the carry-in is to be propagated to the carry-out of the cur- rent lut or if the carry-out needs to be generated. if the carry-out needs to be generated, this is provided by the second lut output. the result of this selection is placed on the carry-out signal, which is connected to the next lut carry-in or the cout/fcout signal, if it is the last lut (k 7 /k 3 ). both of these outputs can be any equation created from k z [1] and k z [0], but in this case, they have been set to the propagate and gener- ate functions. the third lut output creates the result bit for each lut output connected to f[7:0]/f[3:0]. if an adder/subtrac- tor is needed, the control signal to select addition or subtraction is input on f5a/f5c inputs. these inputs generate the controller input as. when as = 0, this function performs the adder, a + b. when as = 1, the function performs the subtractor, a C b. the result bit is created in one-half of the lut from a single bit from each input bus k z [1:0], along with the ripple input bit. the second submode is the counter submode (see figure 10). the present count, which may be initialized via the pfu din inputs to the latches/ffs, is supplied to input k z [0], and then output f[7:0]/f[3:0] will either be incremented by one for an up counter or decre- mented by one for a down counter. if an up/down counter is needed, the control signal to select the direc- tion (up or down) is input on f5a and f5c. when f5[a:c], respectively per nibble, is a logic 1, this indi- cates a down counter and a logic 0 indicates an up counter. 5-5756(f) figure 10. counter submode f7 k 7 [0] k7 dq c c dq q7 regcout cout f6 k 6 [0] k6 dq q6 f4 k 4 [0] k4 dq q4 f3 k 3 [0] k3 dq q3 f2 k 2 [0] k2 dq q2 f1 k 1 [0] k1 dq q1 f5 k 5 [0] k5 dq q5 f0 k 0 [0] k0 dq q0 cin/fcin fcout
18 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas programmable logic cells (continued) in the third submode, multiplier submode , a single pfu can affect an 8x1 bit (4x1 for half-ripple mode) multiply and sum with a partial product (see figure 11). the multiplier bit is input at f5[a:c], respectively per nibble, and the multiplicand bits are input at k z [1], where k 7 [1] is the most significant bit (msb). k z [0] con- tains the partial product (or other input to be summed) from a previous stage. if f5[a:c] is logical 1, the multi- plicand is added to the partial product. if f5[a:c] is log- ical 0, 0 is added to the partial product, which is the same as passing the partial product. cin/fcin can bring the carry-in from the less significant pfus if the multiplicand is wider than 8 bits, and cout/fcout holds any carry-out from the multiplication, which may then be used as part of the product or routed to another pfu in multiplier mode for multiplicand width expan- sion. ripple modes fourth submode features equality comparators . the functions that are explicitly available are a 3 b, a 1 b, and a b, where the value for a is input on k z [0], and the value for b is input on k z [1]. a value of 1 on the carry-out signals valid argument. for example, a carry-out equal to 1 in ab submode indi- cates that the value on k z [0] is greater than or equal to the value on k z [1]. conversely, the functions a b, a + b, and a > b are available using the same functions but with a 0 output expected. for example, a > b with a 0 output indicates a b. table 5 shows each function and the output expected. if larger than 8 bits, the carry-out signal can be cas- caded using fast-carry logic to the carry-in of any adja- cent pfu. the use of this submode could be shown using figure 9, except that the cin/fcin input for the least significant pfu is controlled via configuration. table 5. ripple mode equality comparator functions and outputs 5-5757(f) key: c = configuration data. note: f5[a:c] shorted together. figure 11. multiplier submode equality function orca foundry submode true, if carry-out is: a 3 ba 3 b1 a ba b1 a 1 ba 1 b1 a < b a > b 0 a > b a < b 0 a = b a 1 b0 k7[1] k7[0] + d q c c dq 1 00 k7 f5[a:c] k4[1] k4[0] + d q 1 00 k4 k3[1] k3[0] + d q 1 00 k3 k2[1] k2[0] + d q 1 00 k2 k1[1] k1[0] + d q 1 00 k1 k6[1] k6[0] + d q 1 00 k6 k5[1] k5[0] + d q 1 00 k5 k0[1] k0[0] + d q 1 00 k0 q0 f0 q1 f1 q2 f2 q3 f3 q4 f4 q5 f5 q6 f6 q7 f7 cout regcout
lucent technologies inc. 19 preliminary data sheet august 2000 orca series 4 fpgas programmable logic cells (continued) memory mode the series 4 pfu can be used to implement a 32 x 4 (128-bit) synchronous, dual-port ram. a block diagram of a pfu in memory mode is shown in figure 12. this ram can also be configured to work as a single-port memory and because initial values can be loaded into the ram during configuration, it can also be used as a rom. 5-5969(f)a 1. clk[0:1] are commonly connected in memory mode. 2. ce1 = write enable = wren; wren = 0 (no write enable); wren = 1 (write enabled). ce0 = write port enable 0; ce0 = 0, wren = 0; ce0 = 1, wren = ce1. lsr0 = write port enable 1; lsr0 = 0, wren = ce0; lsr0 = 1, wren = ce1. figure 12. memory mode q6 q4 q2 q0 d 5 q cin(wa1) k z [3:0] 4 f5[a:d] d q din7(wa3) d q din5(wa2) d q din3(wa1) d q din1(wa0) d q din6(wd3) d q din4(wd2) d q din2(wd1) d q din0(wd0) d q ce0, lsr0 s/e clk[0:1] 4 write write read read 4 f6 f4 f2 f0 d q d q d q d q write ram clock address[4:0] address[4:0] data[3:0] data[3:0] enable (see note 2.) ce1
20 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas programmable logic cells (continued) the pfu memory mode uses all luts and latches/ffs including the ninth ff in its implementation as shown in figure 12. the read address is input at the k z [3:0] and f5[a:d] inputs where k z [0] is the lsb and f5[a:d] is the msb, and the write address is input on cin (msb) and din[7, 5, 3, 1], with din[1] being the lsb. write data is input on din[6, 4, 2, 0], where din[6] is the msb, and read data is available combinatorially on f[6, 4, 2, 0] and registered on q[6, 4, 2, 0] with f[6] and q[6] being the msb. the write enable controlling ports are input on ce0, ce1, and lsr0. ce1 is the active- high write enable (ce1 = 1, ram is write enabled). the first write port is enabled by ce0. the second write port is enabled with lsr0. the pfu clk (clk0) signal is used to synchronously write the data. the polarities of the clock, write enable, and port enables are all pro- grammable. write-port enables may be disabled if they are not to be used. data is written to the write data, write address, and write enable registers on the active edge of the clock, but data is not written into the ram until the next clock edge one-half cycle later. the read port is actually asynchronous, providing the user with read data very quickly after setting the read address, but timing is also provided so that the read port may be treated as fully synchronous for write then read applications. if the read and write address lines are tied together (main- taining msb to msb, etc.), then the dual-port ram operates as a synchronous single-port ram. if the write enable is disabled, and an initial memory contents is provided at configuration time, the memory acts as a rom (the write data and write address ports and write port enables are not used). wider memories can be created by operating two or more memory mode pfus in parallel, all with the same address and control signals, but each with a different nibble of data. to increase memory word depth above 32, two or more plcs can be used. figure 10 shows a 128 x 8 dual-port ram that is implemented in eight plcs. this figure demonstrates data path width expan- sion by placing two memories in parallel to achieve an 8-bit data path. depth expansion is applied to achieve 128 words deep using the 32-word deep pfu memo- ries. in addition to the pfu in each plc, the slic (described in the next section) in each plc is used for read address decodes and 3-state drivers. the 128 x 8 ram shown could be made to operate as a single-port ram by tying (bit-for-bit) the read and write addresses. to achieve depth expansion, one or two of the write address bits (generally the msbs) are routed to the write port enables as in figure 10. for 2 bits, the bits select which 32-word bank of ram of the four available from a decode of two wpe inputs is to be written. simi- larly, 2 bits of the read address are decoded in the slic and are used to control the 3-state buffers through which the read data passes. the write data bus is common, with separate nibbles for width expan- sion, across all plcs, and the read data bus is com- mon (again, with separate nibbles) to all plcs at the output of the 3-state buffers. figure 13 also shows the capability to provide a read enable for rams/roms using the slic cell. the read enable will 3-state the read data bus when inactive, allowing the write data and read data buses to be tied together if desired.
preliminary data sheet august 2000 lucent technologies inc. 21 orca series 4 fpgas programmable logic cells (continued) 5-5749(f) figure 13. memory mode expansion example128 x 8 ram rd[7:0] we wa[6:0] ra[6:0] clk wa ra wpe 1 wpe 2 we wd[7:4] 5 5 4 plc 8 wd[7:0] 8 7 7 wa ra wpe 1 wpe 2 we rd[3:0] wd[3:0] 5 5 4 plc rd[7:4] wa ra wpe 1 wpe 2 we wd[7:4] 5 5 4 plc wa ra wpe 1 wpe 2 we rd[3:0] wd[3:0] 5 5 4 plc rd[7:4] re re 4 re 4 re 4 re 4 supplemental logic and interconnect cell each plc contains a slic embedded within the plc routing, outside of the pfu. as its name indicates, the slic performs both logic and interconnect (routing) functions. its main features are 3-statable, bidirectional buffers, and a pa l -like decoder capability. figure 14 shows a diagram of a slic with all of its features shown. all modes of the slic are not available at one time. the ten slic inputs can be sourced directly from the pfu or from the general routing fabric. si[0:9] inputs can come from the horizontal or vertical routing and i[0:9} comes from the pfu outputs o[9:0]. these inputs can also be tied to a logical 1 or 0 constant. the inputs are twin-quad in nature and are segregated into two groups of four nibbles and a third group of two inputs for control. each input nibble groups also have 3-state capability; however, the third pair does not. there is one 3-state control (tri) for each slic, with the capability to invert or disable the 3-state control for each group of four bidis. separate 3-state control for each nibble-wide group is achievable by using the slics decoder (dec) output, driven by the group of two bidis, to control the 3-state of one bidi nibble while using the tri signal to control the 3-state of the other bidi nibble. figure 15 shows the slic in buffer mode with available 3-state control from the tri and dec signals. if the entire slic is acting in a buffer capacity, the dec output may be used to generate a constant logic 1 (vhi) or logic 0 (vlo) signal for gen- eral use. the slic may also be used to generate pa l -like and- or with optional invert (aoi) functions or a decoder of up to 10 bits. each group of buffers can feed into an and gate (4-input and for the nibble groups and 2-input and for the other two buffers). these and gates then feed into a 3-input gate that can be config- ured as either an and gate or an or gate. the output of the 3-input gate is invertible and is output at the dec output of the slic. figure 19 shows the slic in full decoder mode. the functionality of the slic is parsed by the two nibble-wide groups and the 2-bit buffer group. each of these groups may operate independently as bidi buff- ers (with or without 3-state capability for the nibble- wide groups) or as a pa l /decoder.
22 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas programmable logic cells (continued) as discussed in the memory mode section, if the slic is placed into one of the modes where it contains both buffers and a decode or aoi function (e.g., buf_buf_dec mode), the dec output can be gated with the 3-state input signal. this allows up to a 6-input decode (e.g., buf_dec_dec mode) plus the 3-state input to control the enable/disable of up to four buffers per slic. figure 15figure 19 show several configu- rations of the slic, while table 6 shows all of the possi- ble modes. table 6. slic modes 5-5744(f).a. figure 14. slic all modes diagram mode no. mode buf [3:0] buf [7:4] buf [9:8] 1 buffer buffer buffer buffer 2 buf_buf_dec buffer buffer decoder 3 buf_dec_buf buffer decoder buffer 4 buf_dec_dec buffer decoder decoder 5 dec_buf_buf decoder buffer buffer 6 dec_buf_dec decoder buffer decoder 7 dec_dec_buf decoder decoder buffer 8 decoder decoder decoder decoder sin9 i9 sout09 dec dec 0/1 0/1 tri 0/1 0/1 sout08 sout07 sout06 sout05 sout04 sout03 sout02 sout01 sout00 logic 1 or 0 sin8 i8 logic 1 or 0 sin7 i7 logic 1 or 0 sin6 i6 logic 1 or 0 sin5 i5 logic 1 or 0 sin4 i4 logic 1 or 0 sin3 i3 logic 1 or 0 sin2 i2 logic 1 or 0 sin1 i1 logic 1 or 0 sin0 i0 logic 1 or 0
lucent technologies inc. 23 preliminary data sheet august 2000 orca series 4 fpgas programmable logic cells (continued) 5-5745(f).a figure 15. buffer mode 5-5746(f).a figure 16. buffer-buffer-decoder mode sout08 tri 0/1 0/1 1 0 dec this can be used to generate a v hi or v lo . sin8 i8 logic 1 or 0 sout09 sin9 i9 logic 1 or 0 sout07 sin7 i7 logic 1 or 0 sout06 sin6 i6 logic 1 or 0 sout05 sin5 i5 logic 1 or 0 sout04 sin4 i4 logic 1 or 0 sout03 sin3 i3 logic 1 or 0 sout02 sin2 i2 logic 1 or 0 sout01 sin1 i1 logic 1 or 0 sout00 sin0 i0 logic 1 or 0 tri dec 1 1 1 1 sout07 sin7 i7 logic 1 or 0 sout06 sin6 i6 logic 1 or 0 sout05 sin5 i5 logic 1 or 0 sout04 sin4 i4 logic 1 or 0 sin9 i9 logic 1 or 0 sin8 i8 logic 1 or 0 sout03 sin3 i3 logic 1 or 0 sout02 sin2 i2 logic 1 or 0 sout01 sin1 i1 logic 1 or 0 sout00 sin0 i0 logic 1 or 0
24 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas programmable logic cells (continued) 5-5747(f).a figure 17. buffer-decoder-buffer mode 5-5750(f) figure 18. buffer-decoder-decoder mode tri dec 1 1 sout08 sin8 i8 logic 1 or 0 sout09 sin9 i9 logic 1 or 0 sin7 logic 1 or 0 sin6 logic 1 or 0 sin5 logic 1 or 0 sin4 logic 1 or 0 sout03 sin3 i3 logic 1 or 0 sout02 sin2 i2 logic 1 or 0 sout01 sin1 i1 logic 1 or 0 sout00 sin0 i0 logic 1 or 0 if low, then 3 state buffers are high z. dec tri 1 1 sin7 logic 1 or 0 sin6 logic 1 or 0 sin5 logic 1 or 0 sin4 logic 1 or 0 sout03 sin3 i3 logic 1 or 0 sout02 sin2 i2 logic 1 or 0 sout01 sin1 i1 logic 1 or 0 sout00 sin0 i0 logic 1 or 0 sin9 logic 1 or 0 sin8 logic 1 or 0
lucent technologies inc. 25 preliminary data sheet august 2000 orca series 4 fpgas programmable logic cells (continued) 5-5748(f) figure 19. decoder mode plc latches/flip-flops the eight general-purpose latches/ffs in the pfu can be used in a variety of configurations. in some cases, the configuration options apply to all eight latches/ffs in the pfu and some apply to the latches/ffs on a nib- ble-wide basis where the ninth ff is considered inde- pendently. for other options, each latch/ff is independently programmable. in addition, the ninth ff can be used for a variety of functions. table 7 summarizes these latch/ff options. the latches/ffs can be configured as either positive- or negative-level sensitive latches, or positive or negative edge-triggered ffs (the ninth register can only be a ff). all latches/ffs in a given nibble of a pfu share the same clock, and the clock to these latches/ffs can be inverted. the input into each latch/ff is from either the corresponding lut output (f[7:0]) or the direct data input (din[7:0]). the latch/ff input can also be tied to logic 1 or to logic 0, which is the default. table 7. configuration ram controlled latch/ flip-flop operation * not available for ff[8]. each pfu has two independent programmable clocks, clock enable ce[1:0], local set/reset lsr[1:0], and front-end data selects sel[1:0]. when ce is disabled, each latch/ff retains its previous value when clocked. the clock enable, lsr, and sel inputs can be inverted to be active-low. dec sin7 logic 1 or 0 sin6 logic 1 or 0 sin5 logic 1 or 0 sin4 logic 1 or 0 sin9 logic 1 or 0 sin8 logic 1 or 0 sin3 logic 1 or 0 sin1 logic 1 or 0 sin2 logic 1 or 0 sin0 logic 1 or 0 function options common to all latches/ffs in pfu enable gsrn gsrn enabled or has no effect on pfu latches/ffs. set individually in each latch/ff in pfu set/reset mode set or reset. by group (latch/ff[3:0], latch/ff[7:4], and ff[8]) clock enable ce or none. lsr control lsr or none. clock polarity noninverted or inverted. latch/ff mode latch or ff. lsr operation asynchronous or synchronous. front-end select* direct (din[7:0]) or from lut (f[7:0]). lsr priority either lsr or ce has priority.
26 26 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas programmable logic cells (continued) the set/reset operation of the latch/ff is controlled by two parameters: reset mode and set/reset value. when the gsrn and local set/reset (lsr) signals are not asserted, the latch/ff operates normally. the reset mode is used to select a synchronous or asynchronous lsr operation. if synchronous, lsr has the option to be enabled only if clock enable (ce) is active or for lsr to have priority over the clock enable input, thereby set- ting/resetting the ff independent of the state of the clock enable. the clock enable is supported on ffs, not latches. it is implemented by using a 2-input multi- plexer on the ff input, with one input being the previ- ous state of the ff and the other input being the new data applied to the ff. the select of this 2-input multiplexer is clock enable (ce), which selects either the new data or the previous state. when the clock enable is inactive, the ff output does not change when the clock edge arrives. the gsrn signal is only asynchronous, and it sets/ resets all latches/ffs in the fpga based upon the set/ reset configuration bit for each latch/ff. the set/reset value determines whether gsrn and lsr are set or reset inputs. the set/reset value is independent for each latch/ff. an option is available to disable the gsrn function per pfu after initial device configura- tion. the latch/ff can be configured to have a data front- end select. two data inputs are possible in the front- end select mode, with the sel signal used to select which data input is used. the data input into each latch/ff is from the output of its associated lut, f[7:0], or direct from din[7:0], bypassing the lut. in the front-end data select mode, both signals are avail- able to the latches/ffs. if either or both of these inputs is unused or is unavail- able, the latch/ff data input can be tied to a logic 0 or logic 1 instead (the default is logic 0). the latches/ffs can be configured in three basic modes: n local synchronous set/reset: the input into the pfus lsr port is used to synchronously set or reset each latch/ff. n local asynchronous set/reset: the input into lsr asynchronously sets or resets each latch/ff. n latch/ff with front-end select, lsr either synchro- nous or asynchronous: the data select signal selects the input into the latches/ffs between the lut out- put and direct data in. for all three modes, each latch/ff can be indepen- dently programmed as either set or reset. figure 20 provides the logic functionality of the front-end select, global set/reset, and local set/reset operations. the ninth pfu ff, which is generally associated with registering the carry-out signal in ripple mode func- tions, can be used as a general-purpose ff. it is only an ff and is not capable of being configured as a latch. because the ninth ff is not associated with an lut, there is no front-end data select. the data input to the ninth ff is limited to the cin input, logic 1, logic 0, or the carry-out in ripple and half-logic modes. 5-9737(f).a key: c = configuration data. figure 20. latch/ff set/reset configurations ce ce dq s_set s_reset clk set reset f din logic 1 logic 0 lsr cd gsrn ce ce dq clk set reset f din logic 1 logic 0 cd gsrn lsr ce ce dq clk set reset f din logic 1 logic 0 cd gsrn lsr din sel
lucent technologies inc. 27 preliminary data sheet august 2000 orca series 4 fpgas embedded block ram the orca series 4 devices complement the distrib- uted pfu ram with large blocks of memory macro- cells. the memory is available in 512 words by 18 bits/ word blocks with two write and two read ports. two byte lane enables also operate with quad-port functionality. additional logic has been incorporated for fifo, multi- plier, and cam implementations. the ram blocks are organized along the plc rows and are added in pro- portion to the fpga array sizes as shown in table 8. the contents of the ram blocks may be optionally ini- tialized during fpga configuration. table 8. orca series 4 available embedded block ram each highly flexible 512 x 18 (quad-port, two read/two write) ram block can be programmed by the user to meet their particular function. each of the ebr configu- rations use the physical signals as shown in table 9. quad-port addressing permits simultaneous read and write operations. the ebr ports are written synchronously on the posi- tive edge of ckw. synchronous read operations use the positive edge of ckr. options are available to use synchronous read address registers and read output registers, or to bypass these registers and have the ram read operate asynchronously. ebr features quad-port modes (two read/two write) n 512 x 18 with optional built-in arbitration between write ports. n 1024 x 18 built on two blocks with built-in decode logic for simplified implementation and increased speed. dual-port modes (one read/one write) n one 256 x 36. n one 1k x 9. n two 512 x 9 built in one ebr with two separate read, write clocks and enables for independent operation. n two rams with arbitrary number of words whose sum is 512 or less by 18. the joining of ram blocks is supported to create wider and deeper memories. the adjacent routing interface provided by the cibs allow the cascading of blocks together with minimal penalties due to routing delays. fifo modes fifos can be configured to 256, 512, or 1k depths and 36, 18, or 9 widths respectively or two-512 x 9 but also can be expanded using multiple blocks. fifo works synchronously with the same read and write clock where the read port can be registered on the output or not registered. it can also be optionally configured asynchronously with different read and write clocks. integrated flags allow the user the ability to fully utilize the ebr for fifo, without the need to dedicate an address for providing distinct full/empty status. there are four programmable flags provided for each fifo. empty, partially empty, full, and partially full fifo sta- tus. the partially empty and partially full flags are pro- grammable with the flexibility to program the flags to any value from the full or empty threshold. the pro- grammed values can be set to a fixed value through the bit stream, or a dynamic value can be controlled by input pins of the ebr fifo. multiplier modes the orca ebr support two variations of multiplier functions. constant coefficient multiply [kcm] mode will produce a 24-bit output of a fixed 8-bit constant multiply of a 16-bit number or a fixed 16-bit constant multiply of an 8-bit number. this kcm multiplies a con- stant times a 16- or 8-bit number and produces a prod- uct as a 24-bit result. the coefficient and multiplication tables are stored in memory. both the input and outputs can be configured to be registered for pipelining. both write ports are available during multiply mode so that the user logic can update and modify the coeffi- cients for dynamic coefficient updates. an 8 x 8 multiply mode is configurable to either a pipelined or combinatorial multiplier function of two 8-bit numbers. two 8-bit operands are multiplied to yield a 16-bit product. the input and outputs can be registered in pipeline mode. device number of blocks number of ebr bits OR4E2 8 74k or4e4 12 110k or4e6 16 148k or4e10 20 185k or4e14 24 222k
28 28 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas embedded block ram (continued) cam mode the cam block is a content address memory that pro- vides fast address searches by receiving data input and returning addresses that contain the data. imple- mented in each ebr are two 16-word x 8-bit cam function blocks. the cam has three modes: single match, multiple match, and clear, which are all achieved in one clock cycle. in single-match mode, an 8-bit data input is inter- nally decoded and reports a match when data is present in a particular ram address. its result is reported by a corresponding single address bit. in mul- tiple match, the same occurs with the exception of mul- tiple address lines report the match. clear mode is used to clear the cam contents in one clock cycle by erasing all locations.) arbitration logic is optionally programmed by the user to signal occurrences of data collisions as well as to block both ports from writing at the same time. the arbitration logic prioritizes port1. when utilizing the arbiter, the signal busy indicates data is being written to port1. this busy output signals port1 activity by driving a high output. the arbitration default is enabled; however, the user may disable the arbiter in configura- tion. if the arbiter is turned off, both ports could be writ- ten at the same time and the data would be corrupt. in this scenario, the busy signal will indicate a possible error. there is also a user option which dedicates port 1 to communications to the system bus. in this mode the user logic only has access to port0 and arbitration logic is enabled. the system bus utilizes the priority given to it by the arbiter; therefore, the system bus will always be able to write to the ebr. table 9. ram signals port signals i/o function port 0 ar0[#:0] i address to be read. aw0[#:0] i address to be written. bw0<1:0> i byte-write enable. byte = 8 bits + parity bit. <1> = bits[17, 15:9] <0> = bits[16, 7:0] ckr0 i positive-edge asynchronous read clock. ckw0 i positive-edge synchronous write clock. csr0 i enables read to output. active-high. csw0 i enables write to occur. active-high. d [#:0] i input data to be written to ram. q [#:0] o output data of memory contents at referenced address. port 1 ar1[#:0] i address to be read. aw1[#:0] i address to be written. bw1<1:0> i byte-write enable. byte = 8 bits + parity bit. <1> = bits[17, 15:9] <0> = bits[16, 7:0] ckr1 i positive-edge asynchronous read clock. ckw1 i positive-edge synchronous write clock. csr1 i enables read to output. active-high. csw1 i enables write to occur. active-high. d [#:0] i input data to be written to ram. q [#:0] o output data of memory contents at referenced address. control busy o port1 writing. active-high. reset i data output registers cleared. memory contents unaffected. active-low.
lucent technologies inc. 29 preliminary data sheet august 2000 orca series 4 fpgas embedded block ram (continued) 0308 (f) figure 21. ebr read and write cycles with write through table 10. fifo signals port signals i/o function ar(1:0)[9:0] i programs fifo flags. used for partially empty flag size. aw(1:0)[9:0] i programs fifo flags. used for partially full flag size. ff o full flag. pff o partially full flag. pef o partially empty flag. ef o empty flag. d0[17:0] i data inputs for all configurations. d1[17:0] i data inputs for 256 x 36 configurations only. ckw[0:1] i positive-edge write port clock. port 1 only used for 256 x 36 configurations. ckr[0:1] i positive-edge read port clock. port 1 only used for 256 x 36 configurations. csw[1:0] i active-high write enable. port 1 only used for 256 x 36 configurations. csr[1:0] i active-high read enable. port 1 only used for 256 x 36 configurations. reset i active-low. resets fifo pointers. q0[17:0] o data outputs for all configurations. q1[17:0] o data outputs for 256 x 36 configurations. ckwph ckwpl cswsu cswh awh dsu dh bwsu bwh awsu ckwq aq aqh abcd bc a d c ckw csw aw d bw ar q
30 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas embedded block ram (continued) table 11. constant multiplier signals table 12. 8 x 8 multiplier signals table 13. cam signals port signals i/o function ar0[15:0] i data inputoperand. aw(1:0)[8:0] i address bits. d(1:0)[17:0] i data inputs to load memory or change coefficient. ckw[0:1] i positive-edge write port clock. ckr[0:1] i positive-edge read port clock. used for synchronous multiply mode. csw[1:0] i active-high write enable. csr[1:0] i active-high read enable. q[23:0] o data outputsproduct result. port signals i/o function ar0[7:0] i data inputmultiplicand. ar1[7:0] i data inputmultiplier. aw(1:0)[8:0] i address bits for memory. d(1:0)[17:0] i data inputs to load memory. ckw[0:1] i positive-edge write port clock. ckr[0:1] i positive-edge read port clock. used for synchronous multiply mode. csw[1:0] i active-high write enable. csr[1:0] i active-high enables. for enabling address registers. bw(1:0)[1:0] i byte-lane write for loading memory. q[15:0] o data outputsproduct. port signals i/o function ar(1:0)[7:0] i data match. aw(1:0)[8:0] i data write. d(1:0)[17] i clear data active-high. d(1:0)[16] i single match active-high. d(1:0)[3:0] i cam address for data write. csw[1:0] i active-high write enable. enable for cam data write. csr[1:0] i active-high enable data registers. enable for cam data registers. q(1:0)15:0] o decoded data outputs. 1 corresponds to a data match at that address location.
lucent technologies inc. 31 preliminary data sheet august 2000 orca series 4 fpgas routing resources the abundant routing resources of the series 4 archi- tecture are organized to route signals individually or as buses with related control signals. both local and global signals utilize high-speed buffered and nonbuffered routes. one plc segmented (x1), six plc segmented (x6), and bused half-chip (xhl) routes are patterned together to provide high connectivity with fast software routing times and high-speed system performance. x1 routes cross width of one plc and provide local connectivity to pfu and slic inputs and outputs. x6 lines cross width of six plcs and are unidirectional and buffered with taps in the middle and on the end. seg- ments allow connectivity to pfu/slic outputs (driven at one endpoint), other x6 lines (at endpoints), and x1 lines for access to pfu/slic inputs. xh lines run vertically and horizontally the distance of half the device and are useful for driving medium-/long-dis- tance 3-state routing. the improved routing resources offer great flexibility in moving signals to and from the logic core. this flexibil- ity translates into an improved capability to route designs at the required speeds even when the i/o sig- nals have been locked to specific pins. generally, the orca foundry development system is used to automatically route interconnections. interac- tive routing with the orca foundry design editor (epic) is also available for design optimization. the routing resources consist of switching circuitry and metal interconnect segments. generally, the metal lines which carry the signals are designated as routing seg- ments. the switching circuitry connects the routing segments, providing one or more of three basic func- tions: signal switching, amplification, and isolation. a net running from a pfu or pio output (source) to a plc or pio input (destination) consists of one or more routing segments, connected by switching circuitry called configurable interconnect points (cips). clock distribution network primary clock nets the series 4 fpgas provide eight fully distributed glo- bal primary net routing resources. these eight primary nets can only drive clock signals. the scheme dedi- cates four of the eight resources to provide fast primary nets and four are available for general primary nets. the fast primary nets are targeted toward low-skew and small injection times while the general primary nets are also targeted toward low-skew but have more source location flexibility. fast access to the global pri- mary nets can be sourced from two pairs of pads located in the center of each side of the device, from the programmable plls, and dedicated network plls located in the corners, or from plc logic. the i/o pads are dedicated in pairs for use of differential i/o clocking or single-ended i/o clock sources. however, if these pads are not needed to source the clock network, they can be utilized for general i/o. the clock routing scheme is patterned using vertical and horizontal routes which provide connectivity to all plc columns. secondary clock and control nets secondary spines provide flexible clocking and control signaling for local regions. secondary nets usually have high fan-outs. the series 4 utilizes a spine and branches that use additional x6 segments. this strat- egy provides a flexible connectivity and routes can be sourced from any i/o pin, all plls, or from plc logic. edge clock nets routes are distributed around the edges and are avail- able for every four pios (one per pic). all pios and plls can drive the edge clocks and are used in con- junction with the secondary spines discussed above to drive the same edge clock signal into the internal logic array. the edge clocks provide fast injection to the plc array and i/o registers. many edge clock nets are pro- vided on each side of the device. programmable input/output cells programmable i/o the series 4 pio addresses the demand for the flexi- bility to select i/o that meets system interface require- ments. i/os can be programmed in the same manner as in previous orca devices with the addition of new features that allow the user the flexibility to select new i/ o types that support high-speed interfaces. each pic contains up to four programmable i/o pads and are interfaced through a common interface block to the fpga array. the pio group is split into two pairs of i/o pads with each pair having independent clock enables, local set/reset, and global set/reset. on the input side, each pio contains a programmable latch/ff which enables very fast latching of data from any pad. the combination provides for very low setup requirements and zero hold times for signals coming on-chip. it may also be used to demultiplex an input sig- nal, such as a multiplexed address/data signal, and register the signals without explicitly building a demulti- plexer with a pfu.
32 32 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas programmable input/output cells (continued) on the output side of each pio, an output from the plc array can be routed to each output ff, and logic can be associated with each i/o pad. the output logic associ- ated with each pad allows for multiplexing of output sig- nals and other functions of two output signals. the output ff, in combination with output signal multi- plexing, is particularly useful for registering address signals to be multiplexed with data, allowing a full clock cycle for the data to propagate to the output. the out- put buffer signal can be inverted, and the 3-state con- trol can be made active-high, active-low, or always enabled. in addition, this 3-state signal can be regis- tered or nonregistered. the series 4 i/o logic has been enhanced to include modes for speed uplink and downlink capabilities. these modes are supported through shift register logic which divides down incoming data rates or multiplies up outgoing data rates. this new logic block also sup- ports high-speed ddr mode requirements where data is clocked into and out of the i/o buffers on both edges of the clock. the new programmable i/o cell allows designers to select i/os that meet many new communication stan- dards permitting the device to hookup directly without any external interface translation. they support tradi- tional fpga standards as well as high-speed single- ended and differential pair signaling (as shown in table 14). based on a programmable, bank-oriented i/o ring architecture, designs can be implemented using 3.3 v, 2.5 v, 1.8 v, and 1.5 v output levels. table 14. series 4 programmable i/o standards note: interfaces to ddr and zbt memories are supported through the interface standards shown above. standard v ddio (v) v ref (v) interface usage lvttl 3.3 na general purpose. lvcmos2 2.5 na lvcmos1.8 1.8 na pci 3.3 na pci. lvds 2.5 na point to point and multidrop backplanes, high noise immunity. bused-lvds 2.5 na network backplanes, high noise immunity, bus architecture backplanes. lvpecl 2.5 na network backplanes, differential 100 mhz+ clocking, optical transceiver, high-speed networking. pecl 3.3 2.0 backplanes. gtl 3.3 0.8 backplane or processor interface. gtl+ 3.3 1.0 hstl-class i 1.5 0.75 high-speed sram and networking interfaces. htsl-class iii and iv 1.5 0.9 sttl3-class i and ii 3.3 1.5 synchronous dram interface. sstl2-class i and ii 2.5 1.25
lucent technologies inc. 33 preliminary data sheet august 2000 orca series 4 fpgas programmable input/output cells (continued) the pios are located along the perimeter of the device. the pio name is represented by a two-letter designa- tion to indicate on which side of the device it is located followed by a number to indicate in which row or column it is located. the first letter, p, designates that the cell is a pio and not a plc. the second letter indicates the side of the array where the pio is located. the four sides are left (l), right (r), top (t), and bottom (b). the individual i/o pad is indicated by a single letter (either a, b, c, or d) placed at the end of the pio name. as an example, pl10a indicates a pad located on the left side of the array in the tenth row. each pic interfaces to four bond pads and contains the necessary routing resources to provide an interface between i/o pads and the plcs. each pic is com- posed of four programmable i/os and significant routing resources. each pic contains input buffers, output buff- ers, routing resources, latches/ffs, and logic and can be configured as an input, output, or bidirectional i/o. any pio is capable of supporting the i/o standard listed in table 12 and supporting ddr and zbt specifi- cations. the i/o on the or4exxx series devices allows compli- ance with pci local bus (rev. 2.2) 3.3 v signaling environments. the signaling environment used for each input buffer can be selected on a per-pin basis. the selection provides the appropriate i/o clamping diodes for pci compliance. the cibs that bound the pios have significant local routing resources, similar to routing in the plcs. this new routing increases the ability to fix user pinouts prior to placement and routing of a design and still maintain routability. the flexibility provided by the rout- ing also provides for increased signal speed due to a greater variety of optimal signal paths. included in the pio routing interface is a fast path from the input pins to the pfu logic. this feature allows for input signals to be very quickly processed by the slic decoder function and used on-chip or sent back off of the fpga. also, the series 4 pios include latches and ffs and options for using fast, dedicated secondary, and edge clocks. a diagram of a single pio is shown in figure 22, and table 15 provides an overview of the programmable functions in an i/o cell. 5-9732(f) figure 22. series 4 pio image from orca foundry outsh outddmux outdd outffmux outff clk4mux ec sc ce lsrmux lsr gsr enabled disabled srmode ce_over_lsr lsr_over_ce async cemux0 outdd clk outsh clk outdd outreg outreg do ck sp lsr and nand or nor xor xnor plogic pmux outshmux bufmode slew fast levelmode lvcmos18 pci sstl2 sstl3 hstl gtl gtlplus pecl lvpecl lvds p2mux outdd tsmux usrts tsreg do ck lsr reset set pullmode up down none inmux cemuxi normal inverted latchff d0 d1 ck sp lsr d0 ck latchff latch ff inddmux indd inck inff reset set reset set 1 0 0 0 0 1 ec sc delay iopad outmux cell ce 1 lvttl lvcmos2 del0 del1 del2 del3 del0 del1 del2 del3 milliamps six twelve twentyfour resistor off on keepermode off on latch ff
34 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas programmable input/output cells (continued) inputs there are many major options on the pio inputs that can be selected in the orca foundry tools listed in table 15. inputs may have a pull-up or pull-down resis- tor selected on an input for signal stabilization and power management. a weak keeper circuit is also available on inputs. input signals in a pio are passed to cib routing and/or a fast route into the clock routing system. there is also a programmable delay available on the input. when enabled, this delay affects the inff and indd signals of each pio, but not the clock input. the delay allows any signal to have a guaranteed zero hold time when input. this feature is discussed subse- quently. inputs should have transition times of less than 500 ns and should not be left floating. if any pin is not used, it is 3-stated with an internal pull-up resistor enabled automatically after configuration. floating inputs increase power consumption, produce oscillations, and increase system noise. the inputs have a typical hysteresis of approximately 250 mv to reduce sensitivity to input noise. the pic contains input circuitry that provides protection against latch-up and electrostatic discharge. the other features of the pio inputs relate to the latch/ ff structure in the input path. in latch mode, the input signal is fed to a latch that is clocked by either the pri- mary, secondary, or edge clock signal. the clock may be inverted or noninverted. there is also a local set/ reset signal to the latch. the senses of these signals are also programmable and have the capability to enable or disable the global set/reset signal and select the set/reset priority. the same control signals may also be used to control the input latch/ff when it is configured as a ff instead of a latch, with the addition of another control signal used as a clock enable. the pios are paired together and have independent ce, set/reset, and gsrn control signals for the pair. note that these control signals are paired to the same pair of pins used for differential signaling. the input path is also capable of accepting data from any pad using a fast capture feature. this feature can be programmed as a latch or ff referenced to any clock. there are two options for zero-hold input capture in the pio. if input delay mode is selected to delay the signal from the input pin, data can be either registered or latched with guaranteed zero-hold time in the pio using a system clock. to further improve setup time, the fast zero-hold mode of the pio input takes advan- tage of the latch/ff combination and sources the input ff data from a dedicated latch that is clocked by a fast edge clock from the dedicated clock pads or any local pad. the input ff is then driven by a primary clock sourced from a dedicated input pin designed for fast, low-skew operation at the i/os. these dedicated pads are located in pairs in the center of each side of the array and if not utilized by the clock spine can be used as general user i/o. the clock inputs to both the dedi- cated fast capture latch and the input ff can also be driven by the on-chip plls. the combination of input register capability provides for input signal demultiplexing without any additional resources such as for address and data arriving on the same pins. on the positive edge of the clock, the data would come from the pad to latch. the pio input signal is sent to both the input latch and directly to indd. the signal is latched on the falling edge of the clock and output to routing at inff. the address and data are then both available at the rising edge of the clock. these signals may be registered or otherwise pro- cessed in the plcs.
lucent technologies inc. 35 preliminary data sheet august 2000 orca series 4 fpgas programmable input/output cells (continued) table 15. pio options outputs the pios output drivers for ttl/cmos outputs have programmable drive capability and slew rates. two propagation delays (fast, slewlim) are available on out- put drivers. there are three combinations of program- mable drive currents (24 ma sink/12 ma source, 12 ma sink/6 ma, and 6 ma sink/3 ma source). at powerup, the output drivers are in slewlim mode and 12 ma sink/6 ma source. if an output is not to be driven in the selected configuration mode, it is 3-stated. the output buffer signal can be inverted, and the 3-state control signal can be made active-high, active- low, or always enabled. in addition, this 3-state signal can be registered or nonregistered. additionally, there is a fast, open-drain output option that directly connects the output signal to the 3-state control, allowing the out- put buffer to either drive to a logic 0 or 3-state, but never to drive to a logic 1. the pio has both input and output shift register capa- bilities. this ability allows the data rate to be reduced from the pad or increased to the pad by two or four times. the shift register block (srb) is available in groups of four pio. both the input and output shift reg- isters are controlled by the same clock and can operate at the same time at the same speed as long as the srb is not connected to the same pads.the output control signals are similar to the input control signals in that they are per pair of pios. bus hold each pio can be programmed with a keepermode feature. this element is user programmed for bus hold requirements. this mode retains the last known state of a bus when the bus goes into 3-state. it prevents float- ing buses and saves system power. pio register control signals the pio latches/ffs have various clock, clock enable (ce), local set/reset (lsr), and gsrn controls. table 16 provides a summary of these control signals and their effect on the pio latches/ffs. note that all control signals are optionally invertible. the output control sig- nals are similar to the input control signals in that they are per pair of pios. table 16. pio register control signals input option input level lvttl, lvcmos 2, lvcmos 1.8, 3.3 v pci compliant. input speed fast, dela y ed. float value pull-up, pull-down, none. re g ister mode latch, ff, fast zero hold ff, none ( direct input ) . clock sense inverted, noninverted. input selection input 1, input 2, clock input. keeper mode on, off. lvds resistor on, off. output option output drive current 12 ma/6 ma or 6 ma/3 ma 24 ma/12 ma. output function normal, fast open drain. output speed fast, slew. output source ff direct-out, general routin g . output sense active-hi g h, active-low. 3-state sense active-hi g h, active-low ( 3-state ) . ff clockin g ed g e clock, s y stem clock. clock sense inverted, noninverted. logic options see table 17. i/o controls option clock enable active-hi g h, active-low, alwa y s enabled. set/reset level active-hi g h, active-low, no local reset. set/reset t y pe s y nchronous, as y nchronous. set/reset priorit y ce over lsr, lsr over ce. gsr control enable gsr, disable gsr. control signal effect/functionality ed g e clock ( eclk ) clocks input fast-capture latch; optionall y clocks output ff, or 3-state ff. s y stem clock ( sclk ) clocks input latch/ff; optionall y clocks output ff, or 3-state ff. clock enable ( ce ) optionall y enables/disables input ff ( not available for input latch mode ) ; optionall y enables/disables output ff; separate ce inversion capabilit y for input and output. local set/reset ( lsr ) option to disable; affects input latch/ ff, output ff, and 3-state ff if enabled. global set/reset ( gsrn ) option to enable or disable per pio ( the input ff, output ff, and 3-state ff ) after initial confi g uration. set/reset mode the input latch/ff, output ff, and 3-state ff are individuall y set or reset b y both the lsr and gsrn inputs.
36 36 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas programmable input/output cells (continued) the pio output ff can perform output data multiplex- ing with no plc resources required. this type of scheme is necessary for ddr applications which require data clocking out of the i/o on both edges of the clock. in this scheme, the output of outff and outdd are serialized and shifted out on both the posi- tive and negative edges of the clock using the shift reg- isters. the pic logic block can also generate logic functions based on the signals on the outdd and clk ports of the pio. the functions are and, nand, or, nor, xor, and xnor. table 17 is provided as a summary of the pio logic options. table 17. pio lo g ic o p tions flexible i/o features allow the user to select i/o to meet different high-speed interface requirements. these i/os require different input references or supply voltages. the perimeter of the device is divided into groups of pios or buffer banks. for each bank, there is a sepa- rate v ddio . every device is equally broken up into eight i/o banks. the v ddio supplies the correct output volt- age for a particular standard. the user must supply the appropriate power supply to the v ddio pin. within a bank, several i/o standards may be mixed as long as they use a common v ddio . also, some interface stan- dards require a specified threshold voltage known as v ref . in these modes, where a particular v ref is required, the device is automatically programmed to dedicate a pin for the appropriate v ref which must be supplied by the user. the v ref is dedicated exclusively to the bank and cannot be intermixed with other signal- ing requiring other v ref voltages. however, pins not requiring v ref can be mixed in the bank. the v ref pad is then no longer available to the user for general use. see table 14 for a list of the i/o standards supported. table 18. compatible mixed i/o standards 0205(f). figure 23 . orca high-speed i/o banks high-speed memory interfaces pio features allow high-speed interfaces to external sram and/or dram devices. series 4 i/os provide 200 mhz zbt requirements when switching between write and read cycles. zbt allows 100% use of bus cycles during back-to-back read/write and write/read cycles. however, this maximum utilization of the bus increases probability of bus contention when the inter- faced devices attempt to drive the bus to opposite logic values. the lvttl i/o interfaces directly with commer- cial zbt srams signaling and allows the versatility to program the fpga drive strengths from 6 ma to 24 ma. ddr allows data to be read or written on both the rising and the falling edge of the clock which delivers twice the bandwidth. qdr (quad data rate) are similar, but have separate read and write parts for over double the bandwidth. the ddr capability in the pio also allows double the bandwidth per pin for generic transfer of data between two devices. ddr doubles the memory speed from sdrams without the need to increase clock frequency. the flexibility of the pio allows 133 mhz/266 mbits per second performance using the sstl i/o features of the series 4. all ddr interface functions are built into the pio. o p tion descri p tion and output lo g ical and of si g nals on outff and clock. nand output lo g ical nand of si g nals on outff and clock. or output lo g ical or of si g nals on outff and clock. nor output lo g ical nor of si g nals on outff and clock. xor output lo g ical xor of si g nals on outff and clock. xnor output lo g ical xnor of si g nals on outff and clock. v dd io bank volta g e compatible standards 3.3 v lvttl, sstl3-i, sstl3-ii, gtl, gtl+, pecl 2.5 v lvcmos2, sstl2-i, sstl2-ii, lvds, lvpecl 1.8 v lvcmos18 1.5 v hstl i, hstl iii, hstl iv plc array tc tl tr bc bl br cl cr
lucent technologies inc. 37 preliminary data sheet august 2000 orca series 4 fpgas programmable input/output cells (continued) lv d s i / o the lvds differential pair i/o standard allows for high-speed, low-voltage swing and low-power interfaces defined by industry standards: ansi */tia/ eia ? -644 and ieee 1596.3 ssi-lvds. the general-purpose standard is supplied without the need for an input reference supply and uses a low switching voltage which translates to low ac power dissipation. the orca lvds i/o provides an integrated 100 w matching resistor used to provide a differential voltage across the inputs of the receiver. the on-chip integration provides termination of the lvds receiver without the need of dis- crete external board resistors. the user has the programmable option to enable termination per receiver pair for point-to-point applications or, in multipoint interfaces, limit the use of termination to bused pairs. if the user chooses to terminate any differential receiver, a single lvds_r pin is dedicated to connect a single 100 w resistor to v ss , which will provide a balance termination to all of the lvds receiver pairs programmed to termination. see table 20 for the lvds termination pin location. table 19 provides the dc specifications for the orca lvds solution. table 19. lvds i/o specifications table 20. lvds termination pin pio downlink/uplink each group of four pio have access to an input/output shift register as shown in figure 24. this feature allows high- speed input data to be divided down by 1/2 or 1/4, and output data can be multiplied by 2x or 4x its internal speed. both the input and output shift can be programmed to operate at the same time. however, the same pio cannot be used for both input and output shift registers at the same time. for input shift mode, the data from indd from the pio is connected to the input shift register. the input data is divided down and is returned to the routing through the insh nodes. in 4x mode, all the insh nodes are used. 2x mode uses insh4 and insh3. similarly, the output shift register brings data into the register from dedicated outsh nodes. 4x mode uses all the outsh signals. however, only outsh2 and outsh1 are used for 2x mode. * ansi is a registered trademark of american national standards institute, inc. ? eia is a registered trademark of electronic industries association. parameter min typical max unit built-in receiver differential input resistor 95 100 105 w receiver input voltage 0.0 2.4 v differential input threshold C100 100 mv output common-mode voltage 1.125 1.25 1.375 v input common-mode voltage 0.2 1.25 2.2 v dedicated chip lvds external termination pin (lvds_r) per package ba352 bc432 bm680 ac3 ah29 al1
38 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas programmable input/output cells (continued) 0204(f). figure 24. pio shift register indd outsh outdd pio indd outsh outdd pio indd outsh outdd pio indd outsh outdd pio shift register out from fpga shift register into fpga clk outsh1 outsh2 outsh3 outsh4 insh1 intsh2 insh3 insh4 special function blocks internal oscillator the internal oscillator resides in the upper left corner of the fpga array. it has output clock frequencies of 1.25 mhz and 10 mhz. the internal oscillator is the source of the internal cclk used for configuration. it may also be used after configuration as a general- purpose clock signal. global set/reset (gsrn) the gsrn logic resides in the lower-right corner of the fpga. gsrn is an invertible (default active-low) signal that is used to reset all of the user-accessible latches/ ffs on the device. gsrn is automatically asserted at powerup and during configuration of the device. the timing of the release of gsrn at the end of config- uration can be programmed in the start-up logic described below. following configuration, gsrn may be connected to the reset pin via dedicated routing, or it may be connected to any signal via normal routing. within each pfu and pio, individual ffs and latches can be programmed to either be set or reset when gsrn is asserted. series 4 allows individual pfus and pios to turn off the gsrn signal to its latches/ffs after configuration. the reset input pad has a special relationship to gsrn. during configuration, the reset input pad always initiates a configuration abort, as described in the fpga states of operation section. after configura- tion, the gsrn can either be disabled (the default), directly connected to the reset input pad, or sourced by a lower-right corner signal. if the reset input pad is not used as a global reset after configuration, this pad can be used as a normal input pad. start-up logic the start-up logic block can be configured to coordi- nate the relative timing of the release of gsrn, the activation of all user i/os, and the assertion of the done signal at the end of configuration. if a start-up clock is used to time these events, the start-up clock can come from cclk, or it can be routed into the start- up block using lower-right corner routing resources.
lucent technologies inc. 39 preliminary data sheet august 2000 orca series 4 fpgas special function blocks (continued) temperature sensing the built-in temperature-sensing diodes allow junction temperature to be measured during device operation. a physical pin (ptemp) is dedicated for monitoring device junction temperature. ptemp works by forcing a 10 ma current in the forward direction, and then mea- suring the resulting voltage. the voltage decreases with increasing temperature at approximately C1.69 mv/c. a typical device with a 85 c device tem- perature will measure approximately 630 mv. table 21. dedicated temperature sensing boundary-scan the ieee standards 1149.1 and 1149.2 ( ieee stan- dard test access port and boundary-scan architecture) are implemented in the orca series of fpgas. it allows users to efficiently test the interconnection between integrated circuits on a pcb as well as test the integrated circuit itself. the ieee 1149 standard is a well-defined protocol that ensures interoperability among boundary-scan (bscan) equipped devices from different vendors. series 4 fpgas are also compliant to ieee standard 1532/d1. this standard for boundary-scan based in- system configuration of programmable devices pro- vides a standardized programming access and method- ology for fpgas. a device, or set of devices, implementing this standard may be programmed, read back, erased verified, singly or concurrently, with a standard set of resources. the ieee 1149 standards define a test access port (tap) that consists of a four-pin interface with an optional reset pin for boundary-scan testing of inte- grated circuits in a system. the orca series fpga provides four interface pins: test data in (tdi), test mode select (tms), test clock (tck), and test data out (tdo). the prgm pin used to reconfigure the device also resets the boundary-scan logic. the user test host serially loads test commands and test data into the fpga through these pins to drive out- puts and examine inputs. in the configuration shown in figure 26, where boundary-scan is used to test ics, test data is transmitted serially into tdi of the first bscan device (u1), through tdo/tdi connections between bscan devices (u2 and u3), and out tdo of the last bscan device (u4). in this configuration, the tms and tck signals are routed to all boundary-scan ics in parallel so that all boundary-scan components operate in the same state. in other configurations, mul- tiple scan paths are used instead of a single ring. when multiple scan paths are used, each ring is indepen- dently controlled by its own tms and tck signals. figure 26 provides a system interface for components used in the boundary-scan testing of pcbs. the three major components shown are the test host, boundary- scan support circuit, and the devices under test (duts). the duts shown here are orca series fpgas with dedicated boundary-scan circuitry. the test host is normally one of the following: automatic test equipment (ate), a workstation, a pc, or a micropro- cessor. 5-5972(f) key: bsc = boundary-scan cell, bdc = bidirectional data cell, and dcc = data control cell. figure 25. printed-circuit board with boundary- scan circuitry dedicated temperature sensing diode pin per package ba352 bc432 bm680 ab3 ah31 ak4 instruction tdo register bypass register tck tms tdi scan out scan in scan out scan in scan in scan out bsc bdc dcc scan out scan in tapc p_in p_in p_out p_in p_ts p_out p_ts p_in p_out p_ts p_out p_ts pl[ij] pt[ij] pr[ij] pb[ij] bdc dcc plc array bdc dcc bdc dcc bsc bsc bsc see enlarged view below. tms tdi tck tdo tms tdi tck tdo tms tdi tck tdo tms tdi tck tdo u1 u2 u3 u4 tdi tck tdo tms net a net b net c s
40 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas special function blocks (continued) 5-6765(f) figure 26. boundary-scan interface d[7:0] intr micro- processor d[7:0] ce ra r/w dav int sp tms0 tck tdi tdo tdi tms tck tdo orca series fpga tdi orca series fpga tms tck tdo tdi tms tck tdo orca series fpga lucent boundary- scan master (bsm) (dut) (dut) (dut) the boundary-scan support circuit shown in figure 26 is the 497aa boundary-scan master (bsm). the bsm off-loads tasks from the test host to increase test throughput. to interface between the test host and the duts, the bsm has a general mpi and provides paral- lel-to-serial/serial-to-parallel conversion, as well as three 8k data buffers. the bsm also increases test throughput with a dedicated automatic test-pattern generator and with compression of the test response with a signature analysis register. the pc-based boundary-scan test card/software allows a user to quickly prototype a boundary-scan test setup. boundary-scan instructions the series 4 boundary-scan circuitry includes ten ieee 1149.1 , 1149.2, and 1532/d1 instructions and six orca -defined instructions. these also include one ieee 1149.3 optional instruction. a 6-bit wide instruc- tion register supports all the instructions listed in table 22. the bypass instruction passes data inter- nally from tdi to tdo after being clocked by tck. table 22. boundary-scan instructions code instruction 000000 extest 000001 sample 000011 preload 000100 runbist 000101 idcode 000110 usercode 001000 isc_enable 001001 isc_program 001010 isc_noop 001011 isc_disable 001101 isc_program_usercode 001110 isc_read 010001 plc_scan_ring1 010010 plc_scan_ring2 010011 plc_scan_ring3 010100 ram_write 010101 ram_read 111111 bypass
lucent technologies inc. 41 preliminary data sheet august 2000 orca series 4 fpgas special function blocks (continued) the external test (extest) instruction allows the inter- connections between ics in a system to be tested for opens and stuck-at faults. if an extest instruction is performed for the system shown in figure 25, the con- nections between u1 and u2 (shown by nets a, b, and c) can be tested by driving a value onto the given nets from one device and then determining whether this same value is seen at the other device. this is deter- mined by shifting 2 bits of data for each pin (one for the output value and one for the 3-state value) through the bsr until each one aligns to the appropriate pin. then, based upon the value of the 3-state signal, either the i/o pad is driven to the value given in the bsr, or the bsr is updated with the input value from the i/o pad, which allows it to be shifted out tdo. the sample and preload instructions are useful for system debugging and fault diagnosis by allowing the data at the fpgas i/os to be observed during normal operation or written during test operation. the data for all of the i/os is captured simultaneously into the bsr, allowing them to be shifted-out tdo to the test host. since each i/o buffer in the pios is bidirectional, two pieces of data are captured for each i/o pad: the value at the i/o pad and the value of the 3-state control sig- nal. for preload operation, data is written from the bsr to all of the i/os simultaneously. there are six orca -defined instructions. the plc scan rings 1, 2, and 3 (psr1, psr2, psr3) allow user- defined internal scan paths using the plc latches/ffs and routing interface. the ram_write enable (ram_w) instruction allows the user to serially config- ure the fpga through tdi. the ram_read enable (ram_r) allows the user to read back ram contents on tdo after configuration. the idcode instruction allows the user to capture a 32-bit identification code that is unique to each device and serially output it at tdo. the idcode format is shown in table 23. an optional ieee 1149.3 instruction runbist has been implemented. this instruction is used to invoke the built-in self-test (bist) of regular structures like rams, roms, fifos, etc., and the surrounding ran- dom logic in the circuit. also implemented in series 4 devices is the ieee 1532/d1 standards for in-system configuration for pro- grammable logic devices. included are four mandatory and two optional instructions defined in the standards. isc_enable, isc_program, isc_noop, and isc_disable are the four mandatory instructions. isc_enable initializes the devices for all subsequent isc instructions. the isc_program instruction is similar to the ram_write instruction implemented in all orca devices where the user must monitor the pinitn pin for a high indicating the end of initialization and a successful configuration can be started. the isc_program instruction is used to program the configuration memory through a dedicated isc_pdata register. the isc_noop instruction is used when pro- gramming multiple devices in parallel. during this mode, tdi and tdo behave like bypass. the data shifted through tdi is shifted out through tdo. how- ever, the output pins remain in control of the bsr, unlike bypass where they are driven by the system logic. the isc_disable is used upon completion of the isc programming. no new isc instructions will be operable without another isc_enable instruction. optional 1532/d1 instructions include isc_program_usercode. when this instruction is loaded, the user shifts all 32 bits of a user-defined id (lsb first) through tdi. this overwrites any id previ- ously loaded into the id register. this id can then be read back through the usercode instruction defined in ieee 1149.2. isc_read is similar to the orca ram_read instruc- tion which allows the user to read back the configura- tion ram contents serially out on tdo. both must monitor the pdone signal to determine weather or not configuration is completed. isc_read used a 1-bit register to synchronously read back data coming from the configuration memory. the readback data is clocked into the isc_read data register and then clocked out tdo on the falling edge or tck. table 23. series 4e boundary-scan vendor-id codes * plc array size of fpga, reverse bit order. note: table assumes version 0. device version ( 4-bit ) part * ( 10-bit ) famil y ( 6-bit ) manufacturer ( 11-bit ) lsb ( 1-bit ) OR4E2 0000 0011100000 001000 00000011101 1 or4e4 0000 0001010000 001000 00000011101 1 or4e6 0000 0000110000 001000 00000011101 1 or4e10 0000 0011110000 001000 00000011101 1 or4e14 0000 0010001000 001000 00000011101 1
42 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas special function blocks (continued) orca boundary-scan circuitry the orca series boundary-scan circuitry includes a test access port controller (tapc), instruction register (ir), boundary-scan register (bsr), and bypass regis- ter. it also includes circuitry to support the 18 pre- defined instructions. figure 27 shows a functional diagram of the boundary- scan circuitry that is implemented in the orca series. the input pins (tms, tck, and tdi) locations vary depending on the part, and the output pin is the dedi- cated tdo/rd_data output pad. test data in (tdi) is the serial input data. test mode select (tms) controls the boundary-scan test access port controller (tapc). test clock (tck) is the test clock on the board. the bsr is a series connection of boundary-scan cells (bscs) around the periphery of the ic. each i/o pad on the fpga, except for cclk, done, and the boundary- scan pins (tck, tdi, tms, and tdo), is included in the bsr. the first bsc in the bsr (connected to tdi) is located in the first pio i/o pad on the left of the top side of the fpga (pta pio). the bsr proceeds clock- wise around the top, right, bottom, and left sides of the array. the last bsc in the bsr (connected to tdo) is located on the top of the left side of the array (pl1d). the bypass instruction uses a single ff, which resyn- chronizes test data that is not part of the current scan operation. in a bypass instruction, test data received on tdi is shifted out of the bypass register to tdo. since the bsr (which requires a two ff delay for each pad) is bypassed, test throughput is increased when devices that are not part of a test operation are bypassed. the boundary-scan logic is enabled before and during configuration. after configuration, a configuration option determines whether or not boundary-scan logic is used. the 32-bit boundary-scan identification register con- tains the manufacturers id number, unique part num- ber, and version (as described earlier). the identification register is the default source for data on tdo after reset if the tap controller selects the shift- data-register (shift-dr) instruction. if boundary scan is not used, tms, tdi, and tck become user i/os, and tdo is 3-stated or used in the readback operation. an optional usercode is available. the usercode is a 32-bit value that the user can set during device configuration and can be written to and read from the fpga via the boundary-scan logic.
preliminary data sheet august 2000 lucent technologies inc. 43 orca series 4 fpgas special function blocks (continued) 5-5768(f) figure 27. orca series boundary-scan circuitry functional diagram tap controller tms tck boundary-scan register user code registers bypass register data mux instruction decoder instruction register m u x reset clock ir shift-ir update-ir pur tdo select enable reset clock dr shift-dr update-dr tdi data registers psr1/psr2/psr3 registers (plcs) configuration register (ram_r, ram_w) prgm i/o buffers v dd v dd v dd v dd idcode register orca series tap controller (tapc) the orca series tap controller (tapc) is a 1149 compatible test access port controller. the 16 jtag state assignments from the ieee 1149 specification are used. the tapc is controlled by tck and tms. the tapc states are used for loading the ir to allow three basic functions in testing: providing test stimuli (update-dr), providing test execution (run-test/idle), and obtaining test responses (capture-dr). the tapc allows the test host to shift in and out both instructions and test data/results. the inputs and outputs of the tapc are provided in the table below. the outputs are primarily the control signals to the instruction register and the data register. table 24. tap controller input/outputs s y mbol i/o function tms i test mode select tck i test clock pur i powerup reset prgm ibscan reset treset o test lo g ic reset select o select ir ( hi g h ) ; select-dr ( low ) enable o test data out enable capture-dr o capture/parallel load-dr capture-ir o capture/parallel load-ir shift-dr o shift data re g ister shift-ir o shift instruction re g ister update-dr o update/parallel load-dr update-ir o update/parallel load-ir
44 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas special function blocks (continued) the tapc generates control signals that allow capture, shift, and update operations on the instruction and data registers. in the capture operation, data is loaded into the register. in the shift operation, the captured data is shifted out while new data is shifted in. in the update operation, either the instruction register is loaded for instruc- tion decode, or the boundary-scan register is updated for control of outputs. the test host generates a test by providing input into the orca series tms input synchronous with tck. this sequences the tapc through states in order to perform the desired function on the instruction register or a data register. figure 28 provides a diagram of the state transitions for the tapc. the next state is determined by the tms input value. 5-5370(f) figure 28. tap controller state transition diagram select- dr-scan capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr 1 1 0 0 10 run-test/ idle 1 test-logic- reset select- ir-scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir 1 1 0 10 00 0 0 1 0 1 1 1 0 1 1 0 0 0 0 1 11 0 boundary-scan cells figure 29 is a diagram of the boundary-scan cell (bsc) in the orca series pios. there are four bscs in each pio: one for each pad, except as noted above. the bscs are connected serially to form the bsr. the bsc controls the functionality of the in, out, and 3-state signals for each pad. the bsc allows the i/o to function in either the normal or test mode. normal mode is defined as when an out- put buffer receives input from the plc array and pro- vides output at the pad or when an input buffer provides input from the pad to the plc array. in the test mode, the bsc executes a boundary-scan operation, such as shifting in scan data from an upstream bsc in the bsr, providing test stimuli to the pad, capturing test data at the pad, etc. the primary functions of the bsc are shifting scan data serially in the bsr and observing input (p_in), output (p_out), and 3-state (p_ts) signals at the pads. the bsc consists of two circuits: the bidirectional data cell is used to access the input and output data, and the direction control cell is used to access the 3-state value. both cells consist of a ff used to shift scan data which feeds a ff to control the i/o buffer. the bidirec- tional data cell is connected serially to the direction control cell to form a boundary-scan shift register. the tapc signals (capture, update, shiftn, treset, and tck) and the mode signal control the operation of the bsc. the bidirectional data cell is also controlled by the high out/low in (holi) signal generated by the direction control cell. when holi is low, the bidirec- tional data cell receives input buffer data into the bsc. when holi is high, the bsc is loaded with functional data from the plc.
lucent technologies inc. 45 preliminary data sheet august 2000 orca series 4 fpgas special function blocks (continued) the mode signal is generated from the decode of the instruction register. when the mode signal is high (extest), the scan data is propagated to the output buffer. when the mode signal is low (bypass or sample), functional data from the fpgas internal logic is propagated to the output buffer. the boundary-scan description language (bsdl) is provided for each device in the orca series of fpgas on the orca foundry cd. the bsdl is generated from a device profile, pinout, and other boundary-scan information. 5-2844(f) figure 29. boundary-scan cell boundary-scan timing to ensure race-free operation, data changes on specific clock edges. the tms and tdi inputs are clocked in on the rising edge of tck, while changes on tdo occur on the falling edge of tck. in the execution of an extest instruction, parallel data is output from the bsr to the fpga pads on the falling edge of tck. the maximum fre- quency allowed for tck is 10 mhz. figure 30 shows timing waveforms for an instruction scan operation. the diagram shows the use of tms to sequence the tapc through states. the test host (or bsm) changes data on the falling edge of tck, and it is clocked into the dut on the rising edge. d q d q d q d q scan in p_out holi bidirectional data cell i/o buffer direction control cell mode update/tck scan out tck shiftn/capture p_ts p_in pad_in pad_ts pad_out 0 1 0 1 0 1 0 1 0 1
46 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas special function blocks (continued) 5-5971(f) figure 30. instruction register scan timing diagram tck tms tdi run-test/idle run-test/idle exit1-ir exit2-ir update-ir select-dr-scan capture-ir select-ir-scan test-logic-reset shift-ir pause-ir shift-ir exit1-ir readback logic the readback logic can be enabled via a bit stream option or by instantiation of a library readback compo- nent. readback is used to read back the configuration data and, optionally, the state of all pfu and pio ff out- puts. a readback operation can be done while the fpga is in normal system operation. the readback operation can be daisy-chained. to use readback, the user selects options in the bit stream generator in the orca foundry development system. table 25 provides readback options selected in the bit stream generator tool. the table provides the number of times that the configuration data can be read back. this is intended primarily to give the user control over the security of the fpgas configuration program. the user can prohibit readback (0), allow a single readback (1), or allow unrestricted readback (u). table 25. readback options readback can be performed via the series 4 mpi or by using dedicated fpga readback controls. if the mpi is enabled, readback via the dedicated fpga readback logic is disabled. readback using the mpi is discussed in the mpi section. the pins used for dedicated readback are readback data (rd_data), read configuration ( rd_cfg ), and configuration clock (cclk). a readback operation is ini- tiated by a high-to-low transition on rd_cfg . the rd_cfg input must remain low during the readback operation. the readback operation can be restarted at frame 0 by driving the rd_cfg pin high, applying at least two rising edges of cclk, and then driving rd_cfg low again. one bit of data is shifted out on rd_data at the rising edge of cclk. the first start bit of the readback frame is transmitted out several cycles after the first rising edge of cclk after rd_cfg is input low (see the readback timing characteristics table in the timing characteristics section). to be certain of the start of the readback frame, the data can be monitored for the 01 frame start bit pair. o p tion function 0 prohibit readback 1 allow one readback onl y u allow unrestricted number of readbacks
lucent technologies inc. 47 preliminary data sheet august 2000 orca series 4 fpgas special function blocks (continued) readback can be initiated at an address other than frame 0 via the new mpi control registers (see the microprocessor interface section for more information). in all cases, readback is performed at sequential addresses from the start address. it should be noted that the rd_data output pin is also used as the dedicated boundary-scan output pin, tdo. if this pin is being used as tdo, the rd_data output from readback can be routed internally to any other pin desired. the rd_cfg input pin is also used to control the global 3-state (ts_all) function. before and during configuration, the ts_all signal is always driven by the rd_cfg input and readback is disabled. after con- figuration, the selection as to whether this input drives the readback or global 3-state function is determined by a set of bit stream options. if used as the rd_cfg input for readback, the internal ts_all input can be routed internally to be driven by any input pin. the readback frame contains the configuration data and the state of the internal logic. during readback, the value of all registered pfu and pio outputs can be captured. the following options are allowed when doing a capture of the pfu outputs: n do not capture data (the data written to the rams, usually 0, will be read back). n capture data upon entering readback. n capture data based upon a configurable signal inter- nal to the fpga. if this signal is tied to logic 0, cap- ture rams are written continuously. n capture data on either options two or three above. the readback frame has an identical format to that of the configuration data frame, which is discussed later in the configuration data format section. if lut memory is not used as ram and there is no data capture, the readback data (not just the format) will be identical to the configuration data for the same frame. this eases a bitwise comparison between the configuration and readback data. the configuration header, including the length count field, is not part of the readback frame. the readback frame contains bits in locations not used in the configuration. these locations need to be masked out when comparing the configuration and readback frames. the development system optionally provides a readback bit stream to compare to readback data from the fpga. also note that if any of the luts are used as ram and new data is written to them, these bits will not have the same values as the original configuration data frame either. global 3-state control (ts_all) to increase the testability of the orca series fpgas, the global 3-state function (ts_all) disables the device. the ts_all signal is driven from either an external pin or an internal signal. before and during configuration, the ts_all signal is driven by the input pad rd_cfg . after configuration, the ts_all signal can be disabled, driven from the rd_cfg input pad, or driven by a general routing signal in the upper right cor- ner. before configuration, ts_all is active-low; after configuration, the sense of ts_all can be inverted. the following occur when ts_all is activated: n all of the user i/o output buffers are 3-stated. n the tdo/rd_data output buffer is 3-stated. n the rd_cfg , reset , and prgm input buffers remain active with a pull-up. n the done output buffer is 3-stated, and the input buffer is pulled up.
48 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas microprocessor interface (mpi) the series 4 fpgas have a dedicated synchronous mpi function block. the mpi is programmable to operate with powerpc mpc860/mpc8260 series microprocessors. the pin listing is shown in table 26. the mpi implements an 8-, 16-, or 32-bit interface with 4-bit parity to the host processor ( powerpc ) that can be used for configuration and readback of the fpga as well as for user-defined data processing and general monitoring of fpga functions. in addition to dedicated-function registers, the mpi bridges to the amba embedded system bus through which the powerpc bus master can access the fpga configuration logic, ebr, and other user logic. there is also capability to interrupt the host processor either by a hard interrupt or by having the host processor poll the mpi and the embedded system bus. the control portion of the mpi is available following powerup of the fpga if the mode pins specify mpi mode, even if the fpga is not yet configured. the width of the data port is selectable among 8-, 16-, or 32-bit and the parity bus can be 1-, 2-, or 4- bit. in configuration mode, the data bus width and parity are related to the state of the m[0:3] mode pins. for postconfiguration use, the mpi must be included in the configuration bit stream by using an mpi library element in your design from the orca macro library, or by setting the bit of the mpi configuration control register prior to the start of configuration. the user can also enable and disable the parity bus through the configu- ration bit stream. these pads can be used as general i/o when they are not needed for mpi use. the orca fpga is a memory-mapped peripheral to the powerpc processor. the mpi interfaces to the user-pro- grammable fpga logic using the amba embedded system bus. the mpi has access to a series of addressable registers made accessible by the amba system bus that provide fpga control and status, configuration and read- back data transfer, fpga device identification, and a dedicated user scratchpad register. all registers are 8 bits wide. the address map for these registers and the user-logic address space utilize the same registers as the amba embedded system bus. the internal amba bus is 32 bits wide and the proper transformation of 8-, 16-, or 32-bit data of the mpi is done when transferring data between the mpi and esb. table 26. mpc 860 to orca mpi interconnection powerpc signal orca pin name mpi i/o function d[ n :0] d[31:0] i/o 8-, 16-, 32-bit data bus. dp[ m :0] dp[3:0] i/o selectable parity bus width from 1-, 2-, and 4-bit. a[14:31] a[17:0] i 32-bit mpi address bus. ts mpi_strb i transfer start signal. burst mpi_burst i active-low indicates burst transfer in-progress/high indicates current transfer not a burst. cs0 i active-low mpi select. cs1 i active-high mpi select. clkout mpi_clk i powerpc interface clock. rd/wr mpi_rw i read (high)/write (low) signal. ta mpi_ack o active-low transfer acknowledge signal. bdip mpi_bdip o active-low burst transfer in progress signal indicates that the second beat in front of the current one is requested by the master. negated before the burst transfer ends to abort the burst data phase. any of irq [7:0] mpi_irq o active-low interrupt request signal. tea mpi_tea o active-low indicates mpi detects a bus error on the internal system bus for current transaction. retry mpi_rtry o requests the mpc860 to relinquish the bus and retry the cycle.
lucent technologies inc. 49 preliminary data sheet august 2000 orca series 4 fpgas embedded system bus (esb) implemented using the open standard, on-chip bus amba -ahb 2.0 specification, the series 4 devices connects all the fpga elements together with a standardized bus framework. the esb facilitates communication among mpi, configuration, ebrs, and user logic in all the generic fpga devices. ahb serves the need for high-performance soc as well as aligning with current synthesis design flows. multiple bus masters optimize system performance by sharing resources between different bus masters such as the mpi and configuration logic. the wide data bus con- figuration of 32 bits with 4-bit parity supports the high-bandwidth of data-intensive applications of using the wide on- chip memory. amba enhances a reusable design methodology by defining a common backbone for ip modules. the esb is a synchronous bus that is driven by either the mpi clock, internal oscillator, cclk (slave configuration modes), tck (jtag configuration modes), or by a user clock from routing. during initial configuration and reconfig- uration, the bus clock is defaulted to the configuration clock. the postconfiguration clock source is set during config- uration. the user has the ability to program several slaves through the user logic interface. embedded block ram also interfaces seamlessly to the ahb bus. a single bus arbiter controls the traffic on the bus by ensuring that only one master has access to the bus at any time. the arbiter monitors a number of different requests to use the bus and decides which request is currently the highest priority. the configuration modes have the highest priority and overrides all normal user modes. priority can be programmed between mpi and user logic at configuration in generic fpgas. if no priority is set, a round-robin approach is used by granting the next requesting master in a rotating fixed order. several interfaces exist between the esb and other fpga elements. the mpi interface acts as a bridge between the external microprocessor bus and esb. the mpi may have different clock domains than the esb if the esb clock is not sourced from the external microprocessor clock. pipelined operation allows high-speed memory interface to the ebr and peripheral access without the requirement for additional cycles on the bus. burst transfers allow opti- mal use of the memory interface by giving advance information of the nature of the transfers. table 27 is a listing of the esb register file and brief descriptions. table 28 shows the system interrupt registers and table 29 and table 30 show the fpga status and command registers, all with brief descriptions.
50 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas embedded system bus (esb) (continued) table 27. embedded system bus/mpi registers table 28. interrupt register space assignments register byte read/write initial value description 00 0300 ro 32-bit device id 01 0704 r/w scratchpad register 02 0b08 r/w command register 03 0f0c ro status register 04 13 r/w interrupt enable registermpi 12 r/w interrupt enable registeruser 11 r/w interrupt enable registerfpsc 10 ro interrupt cause register 05 1714 r/w readback address register (14 bits) 06 1b18 ro readback data register 07 1f1c r/w configuration data register 08 2320 ro reserved 09 2724 ro bus error address register 0a 2b28 ro interrupt vector 1 predefined by configuration bit stream 0b 2f2c ro interrupt vector 2 predefined by configuration bit stream 0c 3330 ro interrupt vector 3 predefined by configuration bit stream 0d 3734 ro interrupt vector 4 predefined by configuration bit stream 0e 3b38 ro interrupt vector 5 predefined by configuration bit stream 0f 3f3c ro interrupt vector 6 predefined by configuration bit stream 10 4340 top-left ppll control/status 11 4744 top-left hpll control/status 14 5350 top-right ppll control/status 18 6360 bottom-left ppll control/status 19 6764 bottom-left hpll control/status 1c 7370 bottom-right ppll control/status byte bit read/write description 13 7 0 r/w interrupt enable register mpi 12 7 0 r/w interrupt enable register user 11 7 0 r/w interrupt enable registerfpsc 10 interrupt cause registers 7 ro user_irq_general; 6 ro user_irq_slave; 5 ro user_irq_master; 4rocfg_irq_data; 3 ro err_flag 1 2rompi_irq 1 ro fpsc_irq_slave; 0 ro fpsc_irq_master
lucent technologies inc. 51 preliminary data sheet august 2000 orca series 4 fpgas embedded system bus (esb) (continued) table 29. status register space assignments table 30. command register space assignments byte bit read/write description 0f 7:0 reserved 0e 7:0 reserved od 7 ro configuration write data acknowledge 6 ro readback data ready 5 ro unassigned (zero) 4 ro unassigned (zero) 3 ro fpsc_bit_err 2roram_bit_err 1 ro configuration write data size (1, 2, or 4 bytes) 0 ro use with above for hsize[1:0] (byte, half-word, word) 0c 7 ro readback addresses out of range 6 ro error response received by cfg from system bus 5 ro error responses received by cfg from system bus 4 ro unassigned (zero) 3 ro unassigned (zero) 2 ro unassigned (zero) 1 ro err_flag 1 0 ro err_flag 0 byte bit description 08 7 bus reset from mpi > drives hresetn 6 bus reset from user > drives hresetn 5 bus reset from fpsc > drives hresetn 4 sys_daisy 3 repeat_rdbk (don't increment readback address.) 2 mpi_usr_enable 1 readback data size (1, 2, or 4 bytes) 0 use with above for hsize[1:0] 09 7 r/w sys_gsr (gsr input) 6 sys_rd_cfg (similar to fpga pin rd_cfgn, but active-high) 5 prgm from mpi > (similar to fpga pin, but active-high) 4 prgm from user > (similar to fpga pin, but active-high) 3 prgm from fpsc > (similar to fpga pin, but active-high) 2 lock from mpi 1 lock from user 0 lock from fpsc 0a 7:0 reserved 0b 7:0 reserved
52 52 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas phase-locked loops there are eight plls available to perform many clock modification and clock conditioning functions on the series 4 fpgas. six of the plls are programmable allowing the user the flexibility to configure the pll to manipulate the frequency, phase, and duty cycle of a clock signal. four of the programmable plls are capa- ble of manipulating and conditioning clocks from 20 mhz to 200 mhz and two others are capable of manipulating and conditioning clocks from 60 mhz to 420 mhz. frequencies can be adjusted from 1/8x to 8x the input clock frequency. each programmable pll provides two outputs that have different multiplication factors with the same phase relationships. duty cycles and phase delays can be adjusted in 12.5% of the clock period increments. an input buffer delay compen- sation mode is available for phase delay. each ppll provides two outputs (mclk, nclk) that can have pro- grammable (12.5% steps) phase differences. the pplls can be utilized to eliminate skew between the clock input pad and the internal clock inputs across the entire device. the pplls can drive onto the pri- mary, secondary, and edge clock networks inside the fpga. each ppll can take a clock input from the ded- icated pad or differential pair of pads in its corner or from general routing resources. functionality of the pplls is programmed during oper- ation through a read/write interface to the internal sys- tem bus command and status registers or via the configuration bit stream. there is also a pll output sig- nal, lock, that indicates a stable output clock state. unlike series 3, this signal does not have to be inter- grated before use. table 31. ppll specifications additional highly tuned and characterized dedicated phase-locked loops (dplls) are included to ease system designs. these dplls meet itu-t g.811 primary clocking specifications and enable system designers to target very tightly specified clock conditioning not available in the universal pplls. dplls are targeted to low-speed net- working ds1 and e1 and high-speed sonet/sdh networking sts-3 and stm-1 systems. parameter min nom max unit v dd 1.5 1.425 1.5 1.575 v v dd 3.3 3.0 3.3 3.6 v operating temp C40 25 125 c input clock voltage 1.425 1.5 1.575 v output clock voltage 1.425 1.5 1.575 v input clock frequency (no division) ppll 20 200 mhz hppll 60 420 output clock frequency ppll 20 200 mhz hppll 60 420 input duty cycle tolerance 30 70 % output duty cycle 45 50 55 % dc power 28 mw total on current 8.5 ma total off current 30 pa cycle to cycle jitter (p-p) <0.02 uip-p lock time <50 s frequency multiplication 1x, 2x, 3x, 4x, 5x, 6x, 7x, 8x, frequency division 1/8, 1/7, 1/6, 1/5, 1/4, 1/3, 1/2 duty cycle adjust of output clock 12.5, 25, 37.5, 50, 62.5, 75, 87.5 % delay adjust of output clock 0, 12.5, 25, 37.5, 50, 62.5, 75, 87.5 % phase shift between mclk & nclk 0, 45, 90, 135, 180, 225, 270, 315 degree
lucent technologies inc. 53 preliminary data sheet august 2000 orca series 4 fpgas phase-locked loops (continued) table 32 . dpll ds-1/e-1 specifications a dedicated pin pll_vf is needed for externally connecting a low-pass filter circuit, as shown in table 33. this pro- vides the specified dsC1/eC1 pll operating condition. 0203(f). figure 31. pll_vf external requirements table 33. dedicated pin per package parameter min nom max unit v dd 1.5 1.425 1.5 1.575 v v dd 3.3 3.0 3.3 3.6 v operating temp C40 25 125 c input clock voltage 1.425 1.5 1.575 v output clock voltage 1.425 1.5 1.575 v input clock frequency 1.0 2.5 mhz output clock frequency 1.544 mhz 2.048 input duty cycle tolerance 30 70 % output duty cycle 47 50 53 % dc power 20 mw total on current 2.5 ma total off current 40 pa cycle to cycle jitter (p-p) 0.015 at 1.544 mhz uip-p 0.05 at 2.048 mhz lock time <1200 s dedicated pll_vf pin per package ba352 bc432 bm680 b24 c4 d30 p ll _vf c 1 c 2 r 1 r 1 = 64 k w 5% c 1 = 100 pf 5% c 2 = 10,000 pf 5% v ss
54 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas phase-locked loops (continued) table 34. sts-3/stm-1 dpll specifications 0045(f) figure 32. pll naming scheme table 35. phase-lock loops index parameter min nom max unit input clock frequency 155.52 mhz output clock frequency 155.52 mhz input duty cycle tolerance 30 70 % output duty cycle 47 50 53 % dc power 50 mw total on current 2.4 ma total off current 30 pa cycle to cycle jitter (p-p) 0.02 uip-p lock time <50 s name description [ul][ll][ur][lr]ppll universal user-programmable pll (20 mhz200 mhz) [ul][ll]hppll universal user-programmable pll (60 mhz420 mhz) urpll1 ds-1/e-1 dedicated pll lrpll2 sts-1/stm-1 dedicated pll lrppll lrpll2 llppll llhppll urppll urpll1 ulppll ulhppll
preliminary data sheet august 2000 lucent technologies inc. 55 orca series 4 fpgas fpga states of operation prior to becoming operational, the fpga goes through a sequence of states, including initialization, configuration, and start-up. figure 33 outlines these three states. 5-4529(f). figure 33. fpga states of operation C active i/o C release internal reset C done goes high start-up initialization configuration reset or prgm low prgm low C clear configuration memory C init low, hdc high, ldc low operation powerup C power-on time delay C m[3:0] mode is selected C configuration data frame written C init high, hdc high, ldc low C dout active yes no no reset , init , or prgm low bit error yes initialization upon powerup, the device goes through an initialization process. first, an internal power-on-reset circuit is trig- gered when power is applied. dedicated power pins called v dd 33 are used by the configuration logic. when v dd 33 reaches the voltage at which portions of the fpga begin to operate (2.0 v), the i/os are configured based on the configuration mode, as determined by the mode select inputs m[2:0]. a time-out delay is initiated when v dd 33 reaches between 2.7 v to 3.0 v to allow the power supply voltage to stabilize. the init and done outputs are low. at powerup, if v dd 33 does not rise from 2.0 v to v dd 33 in less than 25 ms, the user should delay configuration by inputting a low into init , prgm , or reset until v dd 33 is greater than the recom- mended minimum operating voltage. at the end of initialization, the default configuration option is that the configuration ram is written to a low state. this prevents shorts prior to configuration. as a configuration option, after the first configuration (i.e., at reconfiguration), the user can reconfigure without clearing the internal configuration ram first. the active-low, open-drain initialization signal init is released and must be pulled high by an external resis- tor when initialization is complete. to synchronize the configuration of multiple fpgas, one or more init pins should be wire-anded. if init is held low by one or more fpgas or an external device, the fpga remains in the initialization state. init can be used to signal that the fpgas are not yet initialized. after init goes high for two internal clock cycles, the mode lines (m[3:0]) are sampled, and the fpga enters the configuration state.
56 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas fpga states of operation (continued) the high during configuration (hdc), low during config- uration ( ldc ), and done signals are active outputs in the fpgas initialization and configuration states. hdc, ldc , and done can be used to provide control of external logic signals such as reset, bus enable, or prom enable during configuration. for parallel master configuration modes, these signals provide prom enable control and allow the data pins to be shared with user logic signals. if configuration has begun, an assertion of reset or prgm initiates an abort, returning the fpga to the ini- tialization state. the prgm and reset pins must be pulled back high before the fpga will enter the config- uration state. during the start-up and operating states, only the assertion of prgm causes a reconfiguration. in the master configuration modes, the fpga is the source of configuration clock (cclk). in this mode, the initialization state is extended to ensure that, in daisy- chain operation, all daisy-chained slave devices are ready. independent of differences in clock rates, master mode devices remain in the initialization state an addi- tional six internal clock cycles after init goes high. when configuration is initiated, a counter in the fpga is set to 0 and begins to count configuration clock cycles applied to the fpga. as each configuration data frame is supplied to the fpga, it is internally assem- bled into data words. each data word is loaded into the internal configuration memory. the configuration load- ing process is complete when the internal length count equals the loaded length count in the length count field, and the required end of configuration frame is written. during configuration, the pio and plc latches/ffs are held set/reset and the internal bidi buffers are 3-stated. the combinatorial logic begins to function as the fpga is configured. figure 34 shows the general waveform of the initialization, configuration, and start- up states. configuration the orca series fpga functionality is determined by the state of internal configuration ram. this configura- tion ram can be loaded in a number of different modes. in these configuration modes, the fpga can act as a master or a slave of other devices in the sys- tem. the decision as to which configuration mode to use is a system design issue. configuration is dis- cussed in detail, including the configuration data format and the configuration modes used to load the configu- ration data in the fpga, following a description of the start-up state. start-up after configuration, the fpga enters the start-up phase. this phase is the transition between the config- uration and operational states and begins when the number of cclks received after init goes high is equal to the value of the length count field in the configuration frame and when the end of configuration frame has been written. the system design issue in the start-up phase is to ensure the user i/os become active without inadvertently activating devices in the system or caus- ing bus contention. a second system design concern is the timing of the release of global set/reset of the plc latches/ffs.
lucent technologies inc. 57 preliminary data sheet august 2000 orca series 4 fpgas fpga states of operation (continued) 5-4482(f) figure 34. initialization/configuration/start-up waveforms initialization configuration start-up operation v dd reset prgm init m[3:0] cclk hdc ldc done user i/o internal reset (gsm)
58 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas fpga states of operation (continued) there are configuration options that control the relative timing of three events: done going high, release of the set/reset of internal ffs, and user i/os becoming active. figure 35 shows the start-up timing for orca fpgas. the system designer determines the relative timing of the i/os becoming active, done going high, and the release of the set/reset of internal ffs. in the orca series fpga, the three events can occur in any arbitrary sequence. this means that they can occur before or after each other, or they can occur simulta- neously. there are four main start-up modes: cclk_nosync, cclk_sync, uclk_nosync, and uclk_sync. the only difference between the modes starting with cclk and those starting with uclk is that for the uclk modes, a user clock must be supplied to the start-up logic. the timing of start-up events is then based upon this user clock, rather than cclk. the dif- ference between the sync and nosync modes is that for sync mode, the timing of two of the start-up events, release of the set/reset of internal ffs, and the i/os becoming active is triggered by the rise of the external done pin followed by a variable number of ris- ing clock edges (either cclk or uclk). for the nosync mode, the timing of these two events is based only on either cclk or uclk. done is an open-drain bidirectional pin that may include an optional (enabled by default) pull-up resistor to accommodate wired anding. the open-drain done signals from multiple fpgas can be tied together (anded) with a pull-up (internal or external) and used as an active-high ready signal, an active-low prom enable, or a reset to other portions of the system. when used in sync mode, these anded done pin- scan be used to synchronize the other two start-up events, since they can all be synchronized to the same external signal. this signal will not rise until all fpgas release their done pins, allowing the signal to be pulled high. the default for orca is the cclk_sync synchro- nized start-up mode where done is released on the first cclk rising edge, c1 (see figure 35). since this is a synchronized start-up mode, the open-drain done signal can be held low externally to stop the occurrence of the other two start-up events. once the done pin has been released and pulled up to a high level, the other two start-up events can be programmed individu- ally to either happen immediately or after up to four ris- ing edges of cclk (di, di + 1, di + 2, di + 3, di + 4). the default is for both events to happen immediately after done is released and pulled high. a commonly used design technique is to release done one or more clock cycles before allowing the i/o to become active. this allows other configuration devices, such as proms, to be disconnected using the done signal so that there is no bus contention when the i/os become active. in addition to controlling the fpga during start-up, other start-up techniques that avoid contention include using isolation devices between the fpga and other circuits in the system, reassigning i/o locations, and maintaining i/os as 3-stated outputs until contentions are resolved. each of these start-up options can be selected during bit stream generation in orca foundry, using advanced options. for more information, please see the orca foundry documentation.
lucent technologies inc. 59 preliminary data sheet august 2000 orca series 4 fpgas fpga states of operation (continued) 5-2761(f) figure 35. start-up waveforms di c1 c2 c3 c4 f c1 c2 c3 c4 c1 c2 c3 c4 c1, c2, c3, or c4 di + 1 di di + 2 di + 3 di + 4 di + 1 di di + 2 di + 3 di + 4 orca cclk_sync done in u1 u2 u3 u4 f u1 u2 u3 u4 u1 u2 u3 u4 orca uclk_nosync di di + 1 di + 2 di + 3 orca uclk_sync uclk period synchronization uncertainty done in f c1 c1 u1, u2, u3, or u4 done i/o gsrn active done i/o gsrn active done i/o gsrn active done i/o gsrn active uclk f = finished, no more clks required. cclk f orca cclk_nosync di + 4 di + 3 di + 2 di + 1 period
60 60 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas fpga states of operation (continued) reconfiguration to reconfigure the fpga when the device is operating in the system, a low pulse is input into prgm or a pro- gram command is sent to the system bus . the configura- tion data in the fpga is cleared, and the i/os not used for configuration are 3-stated. the fpga then samples the mode select inputs and begins reconfiguration. when reconfiguration is complete, done is released, allowing it to be pulled high. partial reconfiguration all orca device families have been designed to allow a partial reconfiguration of the fpga at any time. this is done by setting a bit stream option in the previous configuration sequence that tells the fpga to not reset all of the configuration ram during a reconfiguration. then only the configuration frames that are to be modi- fied need to be rewritten, thereby reducing the configu- ration time. other bit stream options are also available that allow one portion of the fpga to remain in operation while a partial reconfiguration is being done. if this is done, the user must be careful to not cause contention between the two configurations (the bit stream resident in the fpga and the partial reconfiguration bit stream) as the second reconfiguration bit stream is being loaded. other configuration options there are many other configuration options available to the user that can be set during bit stream generation in orca foundry. these include options to enable boundary-scan and/or the mpi and/or the programma- ble pll blocks, readback options, and options to con- trol and use the internal oscillator after configuration. other useful options that affect the next configuration (not the current configuration process) include options to disable the global set/reset during configuration, dis- able the 3-state of i/os during configuration, and dis- able the reset of internal rams during configuration to allow for partial configurations (see above). for more information on how to set these and other configuration options, please see the orca foundry documenta- tion. 5-5759(f) figure 36. serial configuration data formatautoincrement mode 5-5760(f) figure 37. serial configuration data formatexplicit mode configuration data configuration data 10 01 01 preamble length id frame configuration configuration postamble configuration header 00 00 count data frame 1 data frame 2 preamble length id frame configuration configuration postamble configuration header address address 00 count data frame 1 data frame 2 frame 2 frame 1 configuration data configuration data 10 01 01 00 00 00
lucent technologies inc. 61 preliminary data sheet august 2000 orca series 4 fpgas fpga states of operation (continued) table 36a. configuration frame format and contents table 36b. configuration frame format and contents for embedded block ram frame contents description header 11110010 preamble for generic fpga. 24-bit length count configuration bit stream length. 11111111 8-bit trailing header. id frame 0101 1111 1111 1111 id frame header. 44 reserved bits reserved bits set to 0. part id 20-bit part id. checksum 8-bit checksum. 11111111 8 stop bits (high) to separate frames. fpga header 1111 0010 this is a new mandatory header for generic portion. 11111111 8 stop bits (high) to separate frames. fpga address frame 00 address frame header. 14-bit address 14-bit address of generic fpga. checksum 8-bit checksum. 11111111 eight stop bits (high) to separate frames. fpga data frame 01 data frame header, same as generic. alignment bits string of 0 bits added to frame to reach a byte boundary. data bits number of data bits depends upon device. checksum 8-bit checksum. 11111111 eight stop bits (high) to separate frames. postamble for generic fpga 00 or 10 postamble header, 00 = finish, 10 = more bits coming. 11111111 111111 dummy address. 11111111 11111111 16 stop bits (high). frame contents description ram header 11110001 a mandatory header for ram bit stream portion. 11111111 8 stop bits (high) to separate frames. ram address frame 00 address frame header, same as generic. 6-bit address 6-bit address of ram blocks. checksum 8-bit checksum. 11111111 eight stop bits (high) to separate frames. ram data frame 01 data frame header. same as generic. 000000 six of 0 bits added to reach a byte boundary. 512x18 data bits exact number of bits in a ram block. checksum 8-bit checksum. 11111111 eight stop bits (high) to separate frames. postamble for ram 00 or 10 postamble header. 00 = finish, 10 = more bits coming. 111111 dummy address. 11111111 11111111 16 stop bits (high).
62 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas fpga states of operation (continued) table 37. configuration frame size devices OR4E2 or4e4 or4e6 or4e10 or4e14 number of frames 1796 2436 3076 3972 4356 data bits/frame 900 1284 1540 1924 2372 maximum configuration data (number of bits/frame x number of frames) 1,610,400 3,127,824 4,737,040 7,642,128 10,332,432 maximum prom size (bits) (add configuration header and postamble) 1,161,648 3,128,072 4,737,288 7,642,376 10,332,680 bit stream error checking there are three different types of bit stream error checking performed in the orca series 4 fpgas: id frame, frame alignment, and crc checking. the id data frame is sent to a dedicated location in the fpga. this id frame contains a unique code for the device for which it was generated. this device code is compared to the internal code of the fpga. any differ- ences are flagged as an id error. this frame is auto- matically created by the bit stream generation program in orca foundry. each data and address frame in the fpga begins with a frame start pair of bits and ends with eight stop bits set to 1. if any of the previous stop bits were a 0 when a frame start pair is encountered, it is flagged as a frame alignment error. error checking is also done on the fpga for each frame by means of a checksum byte. if an error is found on evaluation of the checksum byte, then a checksum/ parity error is flagged. the checksum is the xor of all the data bytes, from the start of frame up to and includ- ing the bytes before the checksum. it applies to the id, address, and data frames. when any of the three possible errors occur, the fpga is forced into an idle state, forcing init low. the fpga will remain in this state until either the reset or prgm pins are asserted. also the pin cfq_irq/mpi_irq is forced low to signal the error and the specific type of bit stream error is written to one of the system bus regis- ters by the fpga configuration logic. the pgrm bit of the system bus control register can also be used to reset out of the error condition and restart configura- tion. fpga configuration modes there are eight methods for configuring the fpga. seven of the configuration modes are selected on the m0, m1, and m2 inputs. the eighth configuration mode is accessed through the boundary-scan interface. a fourth input, m3, is used to select the frequency of the internal oscillator, which is the source for cclk in some configuration modes. the nominal frequencies of the internal oscillator are 1.25 mhz and 10 mhz. the 1.25 mhz frequency is selected when the m3 input is unconnected or driven to a high state. there are three basic fpga configuration modes: master, slave, and peripheral. the configuration data can be transmitted to the fpga serially or in parallel bytes. as a master, the fpga provides the control sig- nals out to strobe data in. as a slave device, a clock is generated externally and provided into the cclk input. in the three peripheral modes, the fpga acts as a microprocessor peripheral. table 38 lists the functions of the configuration mode pins.
lucent technologies inc. 63 preliminary data sheet august 2000 orca series 4 fpgas fpga configuration modes (continued) table 38. configuration modes master parallel mode the master parallel configuration mode is generally used to interface to industry-standard, byte-wide memory. fig- ure 38 provides the connections for master parallel mode. the fpga outputs an 18-bit address on a[17:0] to mem- ory and reads 1 byte of configuration data on the rising edge of rclk. the parallel bytes are internally serialized starting with the least significant bit, d0. d[7:0] of the fpga can be connected to d[7:0] of the microprocessor only if a standard prom file format is used. if a .bit or .rbt file is used from orca foundry, then the user must mirror the bytes in the .bit or .rbt file or leave the .bit or .rbt file unchanged and connect d[7:0] of the fpga to d[0:7] of the microprocessor. 5-9738(f) figure 38. master parallel configuration schematic m3 m2 m1 m0 cclk configuration mode data 0 0 0 0 output. high-frequency. master serial serial 0 1 0 0 output. high-frequency. master parallel 8-bit 0 1 0 1 output. high-frequency. asynchronous peripheral 8-bit 0 1 1 1 na. reserved na 1 0 0 0 output. low-frequency. master serial serial 1 0 0 1 input. slave parallel 8-bit 1 0 1 0 output. mpc860 mpi 8-bit 1 0 1 1 output. mpc860 mpi 16-bit 1 1 0 0 output. low-frequency. master parallel 8-bit 1 1 0 1 output. low-frequency. asynchronous peripheral 8-bit 1 1 1 0 output. mpc860 mpi 32-bit 1 1 1 1 input. slave serial serial a[21:0] d[7:0] eprom oe ce prgm a[21:0] d[7:0] done orca series fpga dout cclk hdc ldc rclk m2 m1 m0 program v dd v dd or gnd to daisy- chained devices
64 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas fpga configuration modes (continued) in master parallel mode, the starting memory address is 00000 hex, and the fpga increments the address for each byte loaded. one master mode fpga can interface to the memory and provide configuration data on dout to additional fpgas in a daisy-chain. the configuration data on dout is provided synchronously with the falling edge of cclk. the frequency of the cclk output is eight times that of rclk. master serial mode in the master serial mode, the fpga loads the configu- ration data from an external serial rom. the configura- tion data is either loaded automatically at start-up or on a prgm command to reconfigure. serial proms can be used to configure the fpga in the master serial mode. configuration in the master serial mode can be done at powerup and/or upon a configure command. the sys- tem or the fpga must activate the serial rom's reset /oe and ce inputs. at powerup, the fpga and serial rom each contain internal power-on reset cir- cuitry that allows the fpga to be configured without the system providing an external signal. the power-on reset circuitry causes the serial rom's internal address pointer to be reset. after powerup, the fpga automati- cally enters its initialization phase. the serial rom/fpga interface used depends on such factors as the availability of a system reset pulse, avail- ability of an intelligent host to generate a configure command, whether a single serial rom is used or mul- tiple serial roms are cascaded, whether the serial rom contains a single or multiple configuration pro- grams, etc. because of differing system requirements and capabilities, a single fpga/serial rom interface is generally not appropriate for all applications. data is read in the fpga sequentially from the serial rom. the data output from the serial rom is con- nected directly into the din input of the fpga. the cclk output from the fpga is connected to the clk input of the serial rom. during the configuration pro- cess, cclk clocks one data bit on each rising edge. since the data and clock are direct connects, the fpga/serial rom design task is to use the system or fpga to enable the reset /oe and ce of the serial rom(s). there are several methods for enabling the serial roms reset /oe and ce inputs. the serial roms reset /oe is programmable to function with reset active-high and oe active-low or reset active- low and oe active-high. in figure 39, serial roms are cascaded to configure multiple daisy-chained fpgas. the host generates a 500 ns low pulse into the fpga's prgm input. the fpgas init input is connected to the serial roms reset /oe input, which has been programmed to function with reset active-low and oe active-high. the fpga done is routed to the ce pin. the low on done enables the serial roms. at the completion of configuration, the high on the fpgas done disables the serial rom. serial roms can also be cascaded to support the con- figuration of multiple fpgas or to load a single fpga when configuration data requirements exceed the capacity of a single serial rom. after the last bit from the first serial rom is read, the serial rom outputs ceo low and 3-states the data output. the next serial rom recognizes the low on ce input and outputs con- figuration data on the data output. after configuration is complete, the fpgas done output into ce disables the serial roms. this fpga/serial rom interface is not used in applica- tions in which a serial rom stores multiple configura- tion programs. in these applications, the next configuration program to be loaded is stored at the rom location that follows the last address for the previ- ous configuration program. the reason the interface in figure 39 will not work in this application is that the low output on the init signal would reset the serial rom address pointer, causing the first configuration to be reloaded. in some applications, there can be contention on the fpga's din pin. during configuration, din receives configuration data, and after configuration, it is a user i/o. if there is contention, an early done at start-up (selected in orca foundry) may correct the problem. an alternative is to use ldc to drive the serial rom's ce pin. in order to reduce noise, it is generally better to run the master serial configuration at 1.25 mhz (m3 pin tied high), rather than 10 mhz, if possible.
lucent technologies inc. 65 preliminary data sheet august 2000 orca series 4 fpgas fpga configuration modes (continued) 5-4456(f) figure 39. master serial configuration schematic asynchronous peripheral mode figure 40 shows the connections needed for the asynchronous peripheral mode. in this mode, the fpga system interface is similar to that of a microprocessor-peripheral interface. the microprocessor generates the control sig- nals to write an 8-bit byte into the fpga. the fpga control inputs include active-low cs0 and active-high cs1 chip selects and wr and rd inputs. the chip selects can be cycled or maintained at a static level during the configura- tion cycle. each byte of data is written into the fpgas d[7:0] input pins. d[7:0] of the fpga can be connected to d[7:0] of the microprocessor only if a standard prom file format is used. if a .bit or .rbt file is used from orca foundry, then the user must mirror the bytes in the .bit or .rbt file or leave the .bit or .rbt file unchanged and connect d[7:0] of the fpga to d[0:7] of the microprocessor. the fpga provides an rdy/ busy status output to indicate that another byte can be loaded. a low on rdy/ busy indicates that the double-buffered hold/shift registers are not ready to receive data, and this pin must be monitored to go high before another byte of data can be written. the shortest time rdy/ busy is low occurs when a byte is loaded into the hold register and the shift register is empty, in which case the byte is immediately transferred to the shift register. the longest time for rdy/ busy to remain low occurs when a byte is loaded into the holding register and the shift register has just started shifting configuration data into configuration ram. the rdy/ busy status is also available on the d7 pin by enabling the chip selects, setting wr high, and applying rd low, where the rd input provides an output enable for the d7 pin when rd is low. the d[6:0] pins are not enabled to drive when rd is low and, therefore, only act as input pins in asynchronous peripheral mode. optionally, the user can ignore the rdy/ busy status and simply wait until the maximum time it would take for the rdy/ busy line to go high, indicating the fpga is ready for more data, before writing the next data byte. din m2 m1 m0 orca series fpga cclk dout to daisy- chained devices data clk ce ceo data clk reset /oe ceo ce to more serial roms as needed done prgm program reset /oe
66 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas fpga configuration modes (continued) 5-9739(f) figure 40. asynchronous peripheral configuration microprocessor interface mode the built-in mpi in series 4 fpgas is designed for use in configuring the fpga. figure 41 show the glueless inter- face for fpga configuration and readback from the powerpc processor. when enabled by the mode pins, the mpi handles all configuration/readback control and handshaking with the host processor. for single fpga configura- tion, the host sets the configuration control register prgm bit to zero then back to a one and, after reading that the configuration write data acknowledge register is high, transfers data 8, 16, or 32 bits at a time to the fpgas d[#:0] input pins. if configuring multiple fpgas through daisy-chain operation is desired, the sys_daisy bit must be set in the configuration control register of the mpi . there are two options for using the host interrupt request in configuration mode. the configuration control register offers control bits to enable the interrupt on either a bit stream error or to notify the host processor when the fpga is ready for more configuration data. the mpi status register may be used in conjunction with, or in place of, the interrupt request options. the status register contains a 2-bit field to indicate the bit stream error status. as previ- ously mentioned, there is also a bit to indicate the mpi s readiness to receive another byte of configuration data. a flow chart of the mpi configuration process is shown in figure 42. micro- prgm orca series fpga dout cclk hdc ldc m2 m1 m0 v dd to daisy- chained devices processor d[7:0] rdy/busy init done address decode logic bus controller 8 cs0 cs1 rd wr
lucent technologies inc. 67 preliminary data sheet august 2000 orca series 4 fpgas fpga configuration modes (continued) 5-5761(f) figure 41. powerpc /mpi configuration schematic configuration readback can also be performed via the mpi when it is in user mode. the mpi is enabled in user mode by setting the mpi_user_enable bit to 1 in the configuration control register prior to the start of configura- tion or through a configuration option. to perform readback, the host processor writes the 14-bit readback start address to the readback address registers and sets the rd_cfg bit to 0 in the configuration control register. read- back data is returned 8 bits at a time to the readback data register and is valid when the data_rdy bit of the status register is 1. there is no error checking during readback. a flow chart of the mpi readback operation is shown in figure 43. the rd_data pin used for dedicated fpga readback is invalid during mpi readback. dout cclk d[#:0] a[17:0] mpi_clk mpi_rw mpi_ack mpi_bdip mpi_irq mpi_strb cs0 cs1 hdc ldc d[#:0] a[14:31] clkout rd/wr ta bdip irq x ts to daisy- chained devices powerpc orca 8, 16, 32 fpga series 4 done init bus controller
68 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas fpga configuration modes (continued) 5-5763(f) figure 42. configuration through mpi power on with write configuration read status register init = 1? no read status register bit stream error? data_rdy = 1? write data to done = 1? done error yes yes yes no no yes no valid m[3:0] control register bits configuration data reg write configuration data register
lucent technologies inc. 69 preliminary data sheet august 2000 orca series 4 fpgas fpga configuration modes (continued) 5-5764(f) figure 43. readback through mpi enable microprocessor set readback address write rd_cfg to 0 data_rdy = 1? read data register start of frame increment address data = 0xff? yes yes read status register in control register 1 interface in user mode read data register found? read until end of frame finished readback? counter in software yes yes write rd_cfg to 1 in control register 1 stop no no error no error no read data register data = 0xff? yes no error
70 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas fpga configuration modes (continued) slave serial mode the slave serial mode is primarily used when multiple fpgas are configured in a daisy-chain (see the daisy chaining section). it is also used on the fpga evaluation board that interfaces to the download cable. a device in the slave serial mode can be used as the lead device in a daisy chain. figure 44 shows the connections for the slave serial configuration mode. the configuration data is provided into the fpgas din input synchronous with the configuration clock cclk input. after the fpga has loaded its configuration data, it retransmits the incoming configuration data on dout. cclk is routed into all slave serial mode devices in parallel. multiple slave fpgas can be loaded with identical configurations simultaneously. this is done by loading the con- figuration data into the din inputs in parallel. 5-4485(f) figure 44. slave serial configuration schematic slave parallel mode the slave parallel mode is essentially the same as the slave serial mode except that 8 bits of data are input on pins d[7:0] for each cclk cycle. due to 8 bits of data being input per cclk cycle, the dout pin does not contain a valid bit stream for slave parallel mode. as a result, the lead device cannot be used in the slave parallel mode in a daisy-chain configuration. figure 45 is a schematic of the connections for the slave parallel configuration mode. wr and cs0 are active-low chip select signals, and cs1 is an active-high chip select signal. these chip selects allow the user to configure mul- tiple fpgas in slave parallel mode using an 8-bit data bus common to all of the fpgas. these chip selects can then be used to select the fpgas to be configured with a given bit stream. the chip selects must be active for each valid cclk cycle until the device has been completely programmed. they can be inactive between cycles but must meet the setup and hold times for each valid positive cclk. d[7:0] of the fpga can be connected to d[7:0] of the microprocessor only if a standard prom file format is used. if a .bit or .rbt file is used from orca foundry, then the user must mirror the bytes in the .bit or .rbt file or leave the .bit or .rbt file unchanged and connect d[7:0] of the fpga to d[0:7] of the microprocessor. micro- processor or download cable m2 m1 m0 hdc series fpga ldc v dd cclk prgm dout to daisy- chained devices done din init orca
lucent technologies inc. 71 preliminary data sheet august 2000 orca series 4 fpgas fpga configuration modes (continued) 5-4487(f) figure 45. slave parallel configuration schematic daisy chaining multiple fpgas can be configured by using a daisy chain of the fpgas. daisy chaining uses a lead fpga and one or more fpgas configured in slave serial mode. the lead fpga can be configured in any mode except slave paral- lel mode. (daisy chaining is available with the boundary-scan ram_w instruction discussed later.) all daisy-chained fpgas are connected in series. each fpga reads and shifts the preamble and length count in on positive cclk and out on negative cclk edges. an upstream fpga that has received the preamble and length count outputs a high on dout until it has received the appropriate number of data frames so that downstream fpgas do not receive frame start bit pairs. after loading and retransmitting the preamble and length count to a daisy chain of slave devices, the lead device loads its config- uration data frames. the loading of configuration data continues after the lead device has received its configuration data if its internal frame bit counter has not reached the length count. when the configuration ram is full and the number of bits received is less than the length count field, the fpga shifts any additional data out on dout. the configuration data is read into din of slave devices on the positive edge of cclk, and shifted out dout on the negative edge of cclk. figure 46 shows the connections for loading multiple fpgas in a daisy-chain configura- tion. the generation of cclk for the daisy-chained devices that are in slave serial mode differs depending on the config- uration mode of the lead device. a master parallel mode device uses its internal timing generator to produce an internal cclk at eight times its memory address rate (rclk). the asynchronous peripheral mode device outputs eight cclks for each write cycle. if the lead device is configured in slave mode, cclk must be routed to the lead device and to all of the daisy-chained devices. micro- processor or system d[7:0] done cclk cs1 m2 m1 m0 hdc ldc 8 v dd init prgm cs0 wr series fpga orca
72 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas fpga configuration modes (continued) 5-4488(f figure 46. daisy-chain configuration schematic v dd eprom program d[7:0] oe ce a[17:0] a[17:0] d[7:0] done m2 m1 m0 done hdc ldc rclk cclk dout din dout din cclk done dout init init init cclk v dd v dd or gnd prgm prgm m2 m1 m0 prgm m2 m1 m0 v dd v dd hdc ldc rclk hdc ldc rclk v dd orca series fpga slave 2 orca series fpga master orca series fpga slave 1 as seen in figure 46, the init pins for all of the fpgas are connected together. this is required to guarantee that powerup and initialization will work correctly. in general, the done pins for all of the fpgas are also connected together as shown to guarantee that all of the fpgas enter the start-up state simultaneously. this may not be required, depending upon the start-up sequence desired. daisy-chaining with boundary scan multiple fpgas can be configured through the jtag ports by using a daisy-chain of the fpgas. this daisy- chaining operation is available upon initial configuration after powerup, after a power-on reset, after pulling the program pin to reset the chip, or during a reconfigura- tion if the en_jtag ram has been set. all daisy-chained fpgas are connected in series. each fpga reads and shifts the preamble and length count in on the positive tck and out on the negative tck edges. an upstream fpga that has received the preamble and length count outputs a high on tdo until it has received the appropriate number of data frames so that downstream fpgas do not receive frame start bit pairs. after loading and retransmitting the preamble and length count to a daisy chain of downstream devices, the lead device loads its configuration data frames. the loading of configuration data continues after the lead device had received its configuration read into tdi of downstream devices on the positive edge of tck, and shifted out tdo on the negative edge of tck. absolute maximum ratings stresses in excess of the absolute maximum ratings can cause permanent damage to the device. these are absolute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operations sections of this data sheet. exposure to absolute maximum ratings for extended periods can adversely affect device reliability. the orca series fpgas include circuitry designed to protect the chips from damaging substrate injection currents and to prevent accumulations of static charge. nevertheless, conventional precautions should be observed during storage, handling, and use to avoid exposure to excessive electrical stress.
lucent technologies inc. 73 preliminary data sheet august 2000 orca series 4 fpgas absolute maximum ratings (continued) table 39. absolute maximum ratings recommended operating conditions table 40. recommended operating conditions note: the maximum recommended junction temperature (t j ) during operation is 125 c. electrical characteristics table 41. electrical characteristics * the pull-up resistor will externally pull the pin to a level 1.0 v below v dd io. parameter symbol min max unit storage temperature t stg C65 150 c power supply voltage with respect to ground v dd 3 4.2 v v dd 15 2 v input signal with respect to ground v ss C 0.3 v ddio + 0.3 v signal applied to high-impedance output v ss C 0.3 v ddio + 0.3 v maximum package body temperature 220 c parameter symbol min max unit power supply voltage with respect to ground v dd 32.7 3.6 v v dd 15 1.4 1.6 v input voltages v in v ss C 0.3 v ddio + 0.3 v junction temperature t j C40 125 c parameter symbol test conditions min max unit input leakage current i l v dd = max, v in = v ss or v dd C10 10 a standby current: OR4E2 or4e4 or4e6 or4e10 or4e14 i ddsb t a = 25 c, v dd = 3.3 v internal oscillator running, no output loads, inputs v dd or gnd (after configuration) tbd tbd tbd tbd tbd ma ma ma ma ma standby current: OR4E2 or4e4 or4e6 or4e10 or4e14 i ddsb t a = 25 c, v dd = 3.3 v internal oscillator stopped, no output loads, inputs v dd or gnd (after configuration) tbd tbd tbd tbd tbd ma ma ma ma ma powerup current: OR4E2 or4e4 or4e6 or4e10 or4e14 ipp power supply current at approximately 1 v, within a recommended power supply ramp rate of 1 ms200 ms tbd tbd tbd tbd tbd ma ma ma ma ma
74 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas electrical characteristics (continued) table 41. electrical characteristics (continued) * the pull-up resistor will externally pull the pin to a level 1.0 v below v dd io. data retention voltage (v dd 33) v dr t a = 25 c 2.3 v input capacitance c in t a = 25 c, v dd = 3.3 v test frequency = 1 mhz 6pf output capacitance c out t a = 25 c, v dd = 3.3 v test frequency = 1 mhz 6pf done pull-up resistor* r done 100 k w m[3:0] pull-up resistor* r m 100 k w i/o pad static pull-up current* i pu v dd io = 3.6 v, v in = v ss , t a = 0 c 14.4 50.9 a i/o pad static pull-down current i pd v dd io = 3.6 v, v in = v ss , t a = 0 c 26 103 a i/o pad pull-up resistor* r pu v dd io = all, v in = v ss , t a = 0 c 100 k w i/o pad pull-down resistor r pd v dd io = all, v in = v dd , t a = 0 c 50 k w done pull-up resistor* r done 100 k w m[3:0] pull-up resistor* r m 100 k w i/o pad static pull-up current* i pu v dd io = 3.6 v, v in = v ss , t a = 0 c 14.4 50.9 a i/o pad static pull-down current i pd v dd io = 3.6 v, v in = v ss , t a = 0 c 26 103 a i/o pad pull-up resistor* r pu v dd io = all, v in = v ss , t a = 0 c 100 k w i/o pad pull-down resistor r pd v dd io = all, v in = v dd , t a = 0 c 50 k w
lucent technologies inc. 75 preliminary data sheet august 2000 orca series 4 fpgas pin information pin descriptions this section describes the pins found on the series 4 fpgas. any pin not described in this table is a user-program- mable i/o. during configuration, the user-programmable i/os are 3-stated with an internal pull-up resistor enabled. if any pin is not used (or not bonded to a package pin), it is also 3-stated with an internal pull-up resistor enabled after configuration. table 42. pin descriptions symbol i/o description dedicated pins v dd 33 3 v positive power supply. v dd 15 1.5 v positive power supply for internal logic. v ddio positive power supply used by i/o banks. gnd ground supply. pll_vf dedicated pins for pll filtering. ptemp i temperature sensing diode pin. dedicated input. reset i during configuration, reset forces the restart of configuration and a pull-up is enabled. after configuration, reset can be used as a general fpga input or as a direct input, which causes all plc latches/ffs to be asynchronously set/reset. cclk i o in the master and asynchronous peripheral modes, cclk is an output which strobes con- figuration data in. in the slave or readback after configuration, cclk is input synchronous with the data on din or d[7:0]. cclk is an output for daisy-chain operation when the lead device is in master, peripheral, or system bus modes. done i as an input, a low level on done delays fpga start-up after configuration.* o as an active-high, open-drain output, a high level on this signal indicates that configura- tion is complete. done has an optional pull-up resistor. prgm i prgm is an active-low input that forces the restart of configuration and resets the bound- ary-scan circuitry. this pin always has an active pull-up. rd_cfg i this pin must be held high during device initialization until the init pin goes high. this pin always has an active pull-up. during configuration, rd_cfg is an active-low input that activates the ts_all function and 3-states all of the i/o. after configuration, rd_cfg can be selected (via a bit stream option) to activate the ts_all function as described above, or, if readback is enabled via a bit stream option, a high-to-low transition on rd_cfg will initiate readback of the configuration data, including pfu output states, starting with frame address 0. rd_data/tdo o rd_data/tdo is a dual-function pin. if used for readback, rd_data provides configura- tion data out. if used in boundary-scan, tdo is test data out. cfg_irq /mpi_irq o during jtag, slave, master, and asynchronous peripheral configuration assertion on this cfg_irq (active-low) indicates an error or errors for block ram or fpsc initialization. mpi active-low interrupt request output. * the fpga states of operation section contains more information on how to control these signals during start-up. the timing of done release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of all user i/os) is controlled by a second set of options.
76 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas pin information (continued) table 42. pin descriptions (continued) symbol i/o description special-purpose pins (can also be used as a general i/o) m[3:0] i during powerup and initialization, m0m3 are used to select the configuration mode with their values latched on the rising edge of init . during configuration, a pull-up is enabled. i/o after configuration, these pins are user-programmable i/o.* pll_ck[0:7] i/o dedicated pcm clock pins. these pins are a user-programmable i/o pins if not used by plls p[tbtr]clk[1:0][ tc] i/o pins dedicated for the primary clock. input pins on the middle of each side with differential pairing. they may be used as general i/o pins if not needed for clocking purposes. tdi, tck, tms i if boundary-scan is used, these pins are test data in, test clock, and test mode select inputs. if boundary-scan is not selected, all boundary-scan functions are inhibited once configuration is complete. even if boundary-scan is not used, either tck or tms must be held at logic 1 during configuration. each pin has a pull-up enabled during configuration. i/o after configuration, these pins are user-programmable i/o.* rdy/busy /rclk o during configuration in peripheral mode, rdy/rclk indicates another byte can be written to the fpga. if a read operation is done when the device is selected, the same status is also available on d7 in asynchronous peripheral mode. after configuration, if the mpi is not used, this pin is a user-programmable i/o pin.* i/o during the master parallel configuration mode, rclk is a read output signal to an external memory. this output is not normally used. hdc o high during configuration is output high until configuration is complete. it is used as a con- trol output, indicating that configuration is not complete. i/o after configuration, this pin is a user-programmable i/o pin.* ldc o low during configuration is output low until configuration is complete. it is used as a control output, indicating that configuration is not complete. i/o after configuration, this pin is a user-programmable i/o pin.* init i/o init is a bidirectional signal before and during configuration. during configuration, a pull-up is enabled, but an external pull-up resistor is recommended. as an active-low open-drain output, init is held low during power stabilization and internal clearing of memory. as an active-low input, init holds the fpga in the wait-state before the start of configuration. after configuration, this pin is a user-programmable i/o pin.* cs0 , cs1 i cs0 and cs1 are used in the asynchronous peripheral, slave parallel, and microprocessor configuration modes. the fpga is selected when cs0 is low and cs1 is high. during con- figuration, a pull-up is enabled. i/o after configuration, these pins are user-programmable i/o pins.* rd /mpi_strb ird is used in the asynchronous peripheral configuration mode. a low on rd changes d7 into a status output. as a status indication, a high indicates ready, and a low indicates busy. wr and rd should not be used simultaneously. if they are, the write strobe overrides. this pin is also used as the mpi data transfer strobe. i/o after configuration, if the mpi is not used, this pin is a user-programmable i/o pin.* * the fpga states of operation section contains more information on how to control these signals during start-up. the timing of done release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration p ins (and the acti- vation of all user i/os) is controlled by a second set of options.
lucent technologies inc. 77 preliminary data sheet august 2000 orca series 4 fpgas special-purpose pins (continued) a[17:0] mpi_burst mpi_bdip mpi_tsz[1:0] a[21:0] i during mpi mode, the a[17:0] are used as the address bus driven by the powerpc bus master utilizing the least significant bits of the powerpc 32-bit address. o during master parallel configuration mode, a[17:0] address the configuration eprom. in mpi mode, many of the a[n] pins have alternate uses as described below. see the special function blocks section for more mpi information. during configuration, if not in master par- allel or an mpi configuration mode, these pins are 3-stated with a pull-up enabled. a[21] is used as the mpi_burst . it is driven low to indicate a burst transfer is in progress. driven high indicates that the current transfer is not a burst. a[22] is used as the mpi_bdip . it is driven by the powerpc processor assertion of this pin indicates that the second beat in front of the current one is requested by the master. negated before the burst transfer ends to abort the burst data phase. a[19:18] are used as the mpi_tsz[1:0] signals and are driven by the bus master to indicate the data transfer size for the transaction. set 01 for byte, 10 for half-word, and 00 for word. during master parallel mode a[21:0], address the configuration eproms up to 4m bytes. if not used for mpi, these pins are user-programmable i/o pins.* mpi_ack oin powerpc mode mpi operation, this is driven low indicating the mpi received the data on the write cycle or returned data on a read cycle. mpi_clk i this is the powerpc synchronous, positive-edge bus clock used for the mpi interface. it can be a source of the clock for the embedded system bus. if mpi is used, this can be the amba bus clock. mpi_tea o a low on the mpi transfer error acknowledge indicates that the mpi detects a bus error on the internal system bus for the current transaction. mpi_rtry o this pin requests the mpc860 to relinquish the bus and retry the cycle. d[31:0] i/o selectable data bus width from 8, 16, 32-bit. driven by the bus master in a write transaction. driven by mpi in a read transaction. i d[7:0] receive configuration data during master parallel, peripheral, and slave parallel con- figuration modes and each pin has a pull-up enabled. during serial configuration modes, d0 is the din input. d[7:3] output internal status for asynchronous peripheral mode when rd is low. after configuration, the pins are user-programmable i/o pins.* dp[3:0] i/o selectable parity bus width from 1, 2, 4-bit, dp[0] for d[7:0], dp[1] for d[15:8], dp[2] for d[23:16], and dp[3] for d[32:24]. after configuration, this pin is a user-programmable i/o pin.* din i during slave serial or master serial configuration modes, din accepts serial configuration data synchronous with cclk. during parallel configuration modes, din is the d0 input. during configuration, a pull-up is enabled. i/o after configuration, this pin is a user-programmable i/o pin.* dout o during configuration, dout is the serial data output that can drive the din of daisy-chained slave devices. data out on dout changes on the rising edge of cclk. i/o after configuration, dout is a user-programmable i/o pin.* symbol i/o description * the fpga states of operation section contains more information on how to control these signals during start-up. the timing of done release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration p ins (and the acti- vation of all user i/os) is controlled by a second set of options. pin information (continued) table 42. pin descriptions (continued)
78 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas pin information (continued) package compatibility table 43 provides the number of user i/os available for the orca series 4 fpgas for each available package. each package has seven dedicated configuration pins. table 43 provides the package pin and pin function for the orca series 4 fpgas and packages. the bond pad name is identified in the pio nomenclature used in the orca foundry design editor. when the number of fpga bond pads exceeds the number of package pins, bond pads are unused. when the number of package pins exceeds the number of bond pads, package pins are left unconnected (no connects). when a package pin is to be left as a no connect for a specific die, it is indicated as a note in the device pad column for the fpga. the tables provide no information on unused pads. table 43. orca i/os summary device 352 pbga 432 ebga 680 pbgam1 or4e6 user i/o single ended 262 306 466 available differential pairs (lvds, lvpecl) 128 150 196 configuration 7 7 7 dedicated function 3 3 3 v dd 15 16 40 48 v dd 33 8 8 8 v dd io 24 24 60 v ss 68 44 88
lucent technologies inc. 79 preliminary data sheet august 2000 orca series 4 fpgas pin information (continued) table 44. or4e6 352-pin pbga pinout ball bank pad function pair* differential ac3 bl lvds_r lvds_r af6 bl pb10c vref l11t_d0 true ae7 bl pb10d d19 l11c_d0 complement af7 bl pb11c d20 l12t_a1 true ad7 bl pb11d d21 l12c_a1 complement ae8 bl pb12c vref l13t_d1 true ac9 bl pb12d d22 l13c_d1 complement af8 bl pb13c d23 l14t_a1 true ad8 bl pb13d d24 l14c_a1 complement ae9 bl pb14c vref l15t_a0 true af9 bl pb14d d25 l15c_a0 complement ae10 bl pb16c d26 l16t_d0 true ad9 bl pb16d d27 l16c_d0 complement ac10 bl pb18c vref l17t_d1 true ae11 bl pb18d d28 l17c_d1 complement ad10 bl pb19c d29 l18t_d1 true af11 bl pb19d d30 l18c_d1 complement ae12 bl pb20c vref l19t_a0 true af12 bl pb20d d31 l19c_a0 complement ad11 bc pb21c l1t_d1 true ae13 bc pb21d l1c_d1 complement ac12 bc pb22c vref l2t_d2 true af13 bc pb22d l2c_d2 complement ad12 bc pb23c pbck0t l3t_d1 true ae14 bc pb23d pbck0c l3c_d1 complement af14 bc pb24c vref l4t_d1 true ad13 bc pb24d l4c_d1 complement ae15 bc pb26c l5t_d0 true ad14 bc pb26d vref l5c_d0 complement af15 bc pb27c l6t_d0 true ae16 bc pb27d l6c_d0 complement * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball.
80 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas ball bank pad function pair* differential ad15 bc pb28c pbck1t l7t_d1 true af16 bc pb28d pbck1c l7c_d1 complement ac15 bc pb29c l8t_d1 true ae17 bc pb29d l8c_d1 complement ae3 bl pb2a dp2 af3 bl pb2c pll_ck6t l6t_a0 true ae4 bl pb2d pll_ck6c l6c_a0 complement af17 bc pb30c l9t_a2 true ac17 bc pb30d vref l9c_a2 complement ae18 bc pb32c l10t_d0 true ad17 bc pb32d vref l10c_d0 complement af18 bc pb34c l11t_d0 true ae19 bc pb34d l11c_d0 complement af19 bc pb35c l12t_d1 true ad18 bc pb35d vref l12c_d1 complement ae20 br pb37c l1t_d1 true ac19 br pb37d l1c_d1 complement af20 br pb38c vref l2t_d1 true ad19 br pb38d l2c_d1 complement ae21 br pb39c l3t_d1 true ac20 br pb39d l3c_d1 complement ad20 br pb40c l4t_d1 true ae22 br pb40d vref l4c_d1 complement af22 br pb42c ad21 br pb43a ae23 br pb44c l5t_d1 true ac22 br pb44d vref l5c_d1 complement af23 br pb45c l6t_d1 true ad22 br pb45d l6c_d1 complement ae24 br pb47c pll_ck5t l7t_d0 true ad23 br pb47d pll_ck5c l7c_d0 complement pin information (continued) table 44. or4e6 352-pin pbga pinout (continued) * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball.
lucent technologies inc. 81 preliminary data sheet august 2000 orca series 4 fpgas ball bank pad function pair* differential ad4 bl pb4c vref l7t_a1 true af4 bl pb4d dp3 l7c_a1 complement ae5 bl pb6c vref l8t_a1 true ac5 bl pb6d d14 l8c_a1 complement af5 bl pb8c d15 l9t_d0 true ae6 bl pb8d d16 l9c_d0 complement ac7 bl pb9c d17 l10t_d0 true ad6 bl pb9d d18 l10c_d0 complement b3 tl pcclk cclk c5 tl pcfg_mpi_irq cfg_irq /mpi_irq c4 tl pdone done j4 tl pl10c cs1 l17t_d1 true h2 tl pl10d cs0 l17c_d1 complement h3 tl pl12c dout l18t_a1 true h1 tl pl12d init l18c_a1 complement j1 tl pl13c a16 l19t_a0 true j2 tl pl13d vref l19c_a0 complement j3 cl pl14c a14 l1t_d0 true k2 cl pl14d a15 l1c_d0 complement k4 cl pl16c d4 l2t_a2 true k1 cl pl16d vref l2c_a2 complement k3 cl pl18c vref l3t_d0 true l2 cl pl18d rdy/busy /rclk l3c_d0 complement m1 cl pl19c a12 l4t_a0 true m2 cl pl19d a13 l4c_a0 complement n2 cl pl21c vref l5t_d1 true l3 cl pl21d a11 l5c_d1 complement n1 cl pl23c vref l6t_d2 true m4 cl pl23d rd /mpi_strb l6c_d2 complement p2 cl pl24c plck0t/scka l7t_d1 true m3 cl pl24d plck0c l7c_d1 complement pin information (continued) table 44. or4e6 352-pin pbga pinout (continued) * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball.
82 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas ball bank pad function pair* differential n3 cl pl25c a9 l8t_d1 true p1 cl pl25d a10 l8c_d1 complement p3 cl pl26c vref l9t_d0 true r2 cl pl26d a8 l9c_d0 complement t2 cl pl28c plck1t/sckb l10t_d0 true r1 cl pl28d plck1c l10c_d0 complement t1 cl pl29c a7 l11t_d1 true r3 cl pl29d vref l11c_d1 complement e4 tl pl2c pll_ck0t l12t_a1 true e2 tl pl2d pll_ck0c l12c_a1 complement u2 cl pl30c a5 l12t_d1 true r4 cl pl30d a6 l12c_d1 complement u4 cl pl32c vref l13t_a2 true u1 cl pl32d wr /mpi_rw l13c_a2 complement u3 cl pl34c vref l14t_d1 true v2 cl pl34d a4 l14c_d1 complement w2 cl pl35c a2 l15t_d0 true v1 cl pl35d a3 l15c_d0 complement v3 cl pl36c a0 l16t_d1 true w1 cl pl36d a1 l16c_d1 complement w4 cl pl37c dp1 l17t_d1 true y2 cl pl37d dp0 l17c_d1 complement w3 bl pl38c vref l1t_d1 true y1 bl pl38d d8 l1c_d1 complement y4 bl pl39c d10 l2t_d1 true aa2 bl pl39d d9 l2c_d1 complement aa1 bl pl40c vref ab1 bl pl42c d12 l3t_a0 true ab2 bl pl42d d11 l3c_a0 complement ac2 bl pl44c d13 l4t_d1 true aa3 bl pl44d vref l4c_d1 complement pin information (continued) table 44. or4e6 352-pin pbga pinout (continued) * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball.
lucent technologies inc. 83 preliminary data sheet august 2000 orca series 4 fpgas ball bank pad function pair* differential ac1 bl pl47c pll_ck7t l5t_d2 true ab4 bl pl47d pll_ck7c l5c_d2 complement e1 tl pl4c d6 l13t_a1 true e3 tl pl4d d5 l13c_a1 complement g4 tl pl6c ldc l14t_d1 true f2 tl pl6d hdc l14c_d1 complement f1 tl pl8c d7 l15t_a1 true f3 tl pl8d l15c_a1 complement g3 tl pl9c a17 l16t_a1 true g1 tl pl9d vref l16c_a1 complement b24 tr pll_vf pll_vf d3 tl pprgrm prgrm g23 tr pr10c l4t_d2 true f26 tr pr10d l4c_d2 complement h24 tr pr11c l3t_d1 true f25 tr pr11d l3c_d1 complement h23 tr pr12c l2t_d2 true g26 tr pr12d l2c_d2 complement j24 tr pr13c l1t_d1 true g25 tr pr13d vref l1c_d1 complement h25 cr pr14c vref l16t_a0 true h26 cr pr14d l16c_a0 complement k24 cr pr15c l15t_d1 true j26 cr pr15d l15c_d1 complement k23 cr pr17c vref l14t_d1 true j25 cr pr17d l14c_d1 complement k26 cr pr18d k25 cr pr19c l13t_d0 true l24 cr pr19d l13c_d0 complement m24 cr pr20c l12t_d1 true l26 cr pr20d l12c_d1 complement pin information (continued) table 44. or4e6 352-pin pbga pinout (continued) * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball.
84 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas ball bank pad function pair* differential m26 cr pr21c l11t_d0 true l25 cr pr21d vref l11c_d0 complement m25 cr pr23c vref l10t_d0 true n24 cr pr23d l10c_d0 complement n26 cr pr24c prck0t l9t_d1 true p24 cr pr24d prck0c l9c_d1 complement n25 cr pr25c l8t_a1 true n23 cr pr25d l8c_a1 complement r23 cr pr26c l7t_d2 true p26 cr pr26d vref l7c_d2 complement t24 cr pr27c prck1t l6t_d1 true p25 cr pr27d prck1c l6c_d1 complement r25 cr pr29c l5t_a0 true r26 cr pr29d vref l5c_a0 complement u24 cr pr30c l4t_d1 true t26 cr pr30d l4c_d1 complement u23 cr pr31c l3t_d1 true t25 cr pr31d vref l3c_d1 complement u25 cr pr33c vref l2t_d0 true v24 cr pr33d l2c_d0 complement v25 cr pr35c l1t_a0 true v26 cr pr35d l1c_a0 complement w26 br pr36c l16t_a1 true w24 br pr36d l16c_a1 complement w25 br pr37c l15t_d1 true v23 br pr37d vref l15c_d1 complement y26 br pr38c l14t_a1 true y24 br pr38d l14c_a1 complement aa26 br pr39c l13t_d0 true y25 br pr39d vref l13c_d0 complement e24 tr pr3c pll_ck3t l8t_d1 true pin information (continued) table 44. or4e6 352-pin pbga pinout (continued) * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball.
lucent technologies inc. 85 preliminary data sheet august 2000 orca series 4 fpgas ball bank pad function pair* differential c25 tr pr3d pll_ck3c l8c_d1 complement y23 br pr40c l12t_d0 true aa24 br pr40d l12c_d0 complement ab26 br pr41c vref l11t_d0 true aa25 br pr41d l11c_d0 complement ab25 br pr43c l10t_a1 true ab23 br pr43d l10c_a1 complement ac24 br pr44c vref l9t_a1 true ac26 br pr44d l9c_a1 complement ad26 br pr46c pll_ck4t l8t_d0 true ac25 br pr46d pll_ck4c l8c_d0 complement e23 tr pr5c l7t_d2 true d26 tr pr5d l7c_d2 complement f24 tr pr7c l6t_d1 true d25 tr pr7d vref l6c_d1 complement e25 tr pr9c vref l5t_a0 true e26 tr pr9d l5c_a0 complement d2 tl prd_cfg rd_cfg c2 tl prd_data rd_data/tdo c1 tl preset reset a7 tl pt10c tms l6t_d2 true d8 tl pt10d d0 l6c_d2 complement b7 tl pt11d vref c9 tl pt13c mpi_tea l5t_d1 true a8 tl pt13d vref l5c_d1 complement b8 tl pt14c m3 l4t_d0 true a9 tl pt14d m2 l4c_d0 complement c10 tl pt15c a21/mpi_burst l3c_d0 true b9 tl pt15d mpi_clk l3c_d0 complement d10 tl pt16c m1 l2t_a2 true a10 tl pt16d m0 l2c_a2 complement pin information (continued) table 44. or4e6 352-pin pbga pinout (continued) * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball.
86 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas ball bank pad function pair* differential b10 tl pt18c mpi_ack l1c_d2 true d12 tl pt18d mpi_rtry l1c_d2 complement a11 tc pt19c vref l13t_d1 true c12 tc pt19d l13c_d1 complement b11 tc pt21c l12t_d0 true a12 tc pt21d vref l12c_d0 complement c13 tc pt22c ptck0t l11t_d0 true b12 tc pt22d ptck0c l11c_d0 complement c14 tc pt23c ptck1t l10t_d1 true a13 tc pt23d ptck1c l10c_d1 complement b13 tc pt24c vref l9t_d1 true c15 tc pt24d l9c_d1 complement a14 tc pt26c l8t_d2 true d15 tc pt26d l8c_d2 complement b14 tc pt28c l7t_d1 true c16 tc pt28d l7c_d1 complement a15 tc pt29c vref l6t_a0 true b15 tc pt29d l6c_a0 complement a4 tl pt2c pll_ck1t l11t_d2 true d5 tl pt2d pll_ck1c l11c_d2 complement c17 tc pt30c l5t_d0 true b16 tc pt30d l5c_d0 complement d17 tc pt32c vref l4t_a2 true a17 tc pt32d l4c_a2 complement c18 tc pt33c l3t_d0 true b17 tc pt33d l3c_d0 complement a18 tc pt34c l2t_a0 true b18 tc pt34d vref l2c_a0 complement c19 tc pt35c l1t_a1 true a19 tc pt35d l1c_a1 complement d18 tr pt36c l16t_d1 true pin information (continued) table 44. or4e6 352-pin pbga pinout (continued) * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball.
lucent technologies inc. 87 preliminary data sheet august 2000 orca series 4 fpgas ball bank pad function pair* differential b19 tr pt36d l16c_d1 complement c20 tr pt38c vref l15t_a1 true a20 tr pt38d l15c_a1 complement b20 tr pt39c l14t_d0 true a21 tr pt39d l14c_d0 complement d20 tr pt40c vref l13t_d1 true b21 tr pt40d l13c_d1 complement a22 tr pt42c l12t_a1 true c22 tr pt42d vref l12c_a1 complement d22 tr pt43c l11t_a1 true b22 tr pt43d l11c_a1 complement a23 tr pt45c l10t_a1 true c23 tr pt45d vref l10c_a1 complement b23 tr pt47c pll_ck2t l9t_a0 true a24 tr pt47d pll_ck2c l9c_a0 complement b4 tl pt4c tck l10t_d2 true c6 tl pt4d tdi l10c_d2 complement a5 tl pt6c d2 l9t_a0 true b5 tl pt6d d1 l9c_a0 complement a6 tl pt8c d3 l8t_d2 true d7 tl pt8d a18/mpi_tsz0 l8c_d2 complement b6 tl pt9c a19/mpi_tsz1 l7t_d2 true c8 tl pt9d a20/mpi_bdip l7c_d2 complement ab3 bl ptemp ptemp aa23 tl v dd 15 aa4 tl v dd 15 ac11 cl v dd 15 ac16 cl v dd 15 ac21 bl v dd 15 ac6 bl v dd 15 d11 bc v dd 15 pin information (continued) table 44. or4e6 352-pin pbga pinout (continued) * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball.
88 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas ball bank pad function pair* differential d16 bc v dd 15 d21 br v dd 15 d6 br v dd 15 f23 cr v dd 15 f4 cr v dd 15 l23 tr v dd 15 l4 tr v dd 15 t23 tc v dd 15 t4 tc v dd 15 b1 tl v dd 33 ad1 bl v dd 33 af2 bl v dd 33 af24 br v dd 33 ae26 br v dd 33 c26 tr v dd 33 a25 tr v dd 33 a3 tl v dd 33 d1 tl v dd io g2 tl v dd io c11 tl v dd io c7 tl v dd io a16 tc v dd io d13 tc v dd io g24 tr v dd io d24 tr v dd io c21 tr v dd io u26 cr v dd io r24 cr v dd io m23 cr v dd io af21 br v dd io ad25 br v dd io ab24 br v dd io pin information (continued) table 44. or4e6 352-pin pbga pinout (continued) * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball.
lucent technologies inc. 89 preliminary data sheet august 2000 orca series 4 fpgas ball bank pad function pair* differential ac14 bc v dd io ad16 bc v dd io y3 bl v dd io ad2 bl v dd io ad5 bl v dd io af10 bl v dd io l1 cl v dd io p4 cl v dd io t3 cl v dd io a1 tl v ss a2 tl v ss a26 tl v ss ac13 tl v ss ac18 tl v ss ac23 tl v ss ac4 tl v ss ac8 tl v ss ad24 tl v ss ad3 cl v ss ae1 cl v ss ae2 cl v ss ae25 cl v ss af1 cl v ss af25 cl v ss af26 cl v ss b2 cl v ss b25 bl v ss b26 bl v ss c24 bl v ss c3 bl v ss d14 bl v ss pin information (continued) table 44. or4e6 352-pin pbga pinout (continued) * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball.
90 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas ball bank pad function pair* differential d19 bl v ss d23 bl v ss d4 bl v ss d9 bl v ss h4 bc v ss j23 bc v ss n4 bc v ss p23 bc v ss v4 bc v ss w23 bc v ss l11 bc v ss l12 bc v ss l13 br v ss l14 br v ss l15 br v ss l16 br v ss m11 br v ss m12 br v ss m13 br v ss m14 br v ss m15 br v ss m16 cr v ss n11 cr v ss n12 cr v ss n13 cr v ss n14 cr v ss n15 cr v ss n16 cr v ss p11 cr v ss p12 tr v ss p13 tr v ss p14 tr v ss pin information (continued) table 44. or4e6 352-pin pbga pinout (continued) * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball.
lucent technologies inc. 91 preliminary data sheet august 2000 orca series 4 fpgas ball bank pad function pair* differential p15 tr v ss p16 tr v ss r11 tr v ss r12 tr v ss r13 tr v ss r14 tr v ss r15 tc v ss r16 tc v ss t11 tc v ss t12 tc v ss t13 tc v ss t14 tc v ss t15 tc v ss t16 tc v ss pin information (continued) table 44. or4e6 352-pin pbga pinout (continued) * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball.
92 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas pin information (continued) table 45. or4e6 432-pin ebga ball bank pad function pair* differential e4 tr v dd 33 d3 tr v dd io d2 tr pr3d pll_ck3c l10c_a0 complement d1 tr pr3c pll_ck3t l10t_a0 true f4 tr pr5d l9c_d0 complement e3 tr pr5c l9t_d0 true e2 tr pr6d l8c_a0 complement e1 tr pr6c l8t_a0 true f3 tr pr7d vref l7c_a0 complement f2 tr pr7c l7t_a0 true f1 tr pr8d l6c_d2 complement h4 tr pr8c l6t_d2 true g3 tr pr9d l5c_a0 complement g2 tr pr9c vref l5t_a0 true g1 tr v dd io j4 tr pr10d l4c_d0 complement h3 tr pr10c l4t_d0 true h2 tr pr11d l3c_d0 complement j3 tr pr11c l3t_d0 true k4 tr pr12d l2c_d1 complement j2 tr pr12c l2t_d1 true j1 tr pr13d vref l1c_d1 complement k3 tr pr13c l1t_d1 true k2 cr pr14d l19c_a0 complement k1 cr pr14c vref l19t_a0 true l3 cr pr15d l18c_d0 complement m4 cr pr15c l18t_d0 true l2 cr pr17d l17c_a0 complement l1 cr pr17c vref l17t_a0 true m3 cr pr18d l16c_d0 complement n4 cr pr18c l16t_d0 true m2 cr pr19d l15c_d0 complement * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball.
lucent technologies inc. 93 preliminary data sheet august 2000 orca series 4 fpgas ball bank pad function pair* differential n3 cr pr19c l15t_d0 true n2 cr v dd io p4 cr pr20d l14c_d2 complement n1 cr pr20c l14t_d2 true p3 cr pr21d vref l13c_a0 complement p2 cr pr21c l13t_a0 true p1 cr pr22d l12c_d1 complement r3 cr pr22c l12t_d1 true r2 cr pr23d l11c_a0 complement r1 cr pr23c vref l11t_a0 true t2 cr pr24d prck0c l10c_a1 complement t4 cr pr24c prck0t l10t_a1 true t3 cr pr25d l9c_d1 complement u1 cr pr25c l9t_d1 true u2 cr v dd io u3 cr pr26d vref l8c_d1 complement v1 cr pr26c l8t_d1 true v2 cr pr27d prck1c l7c_a0 complement v3 cr pr27c prck1t l7t_a0 true w1 cr pr29d vref l6c_d2 complement v4 cr pr29c l6t_d2 true w2 cr pr30d l5c_a0 complement w3 cr pr30c l5t_a0 true y2 cr pr31d vref l4c_d1 complement w4 cr pr31c l4t_d1 true y3 cr v dd io aa1 cr pr32d l3c_a0 complement aa2 cr pr32c l3t_a0 true y4 cr pr33d l2c_d0 complement aa3 cr pr33c vref l2t_d0 true ab1 cr pr35d l1c_a0 complement ab2 cr pr35c l1t_a0 true pin information (continued) table 45. or4e6 432-pin ebga (continued) * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball.
94 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas ball bank pad function pair* differential ab3 br pr36d l19c_d1 complement ac1 br pr36c l19t_d1 true ac2 br pr37d vref l18c_d1 complement ab4 br pr37c l18t_d1 true ac3 br pr38d l17c_d0 complement ad2 br pr38c l17t_d0 true ad3 br pr39d vref l16c_d0 complement ac4 br pr39c l16t_d0 true ae1 br pr40d l15c_a0 complement ae2 br pr40c l15t_a0 true ae3 br pr41d l14c_d0 complement ad4 br pr41c vref l14t_d0 true af1 br v dd io af2 br pr42d l13c_a0 complement af3 br pr42c l13t_a0 true ag1 br pr43d l12c_a0 complement ag2 br pr43c l12t_a0 true ag3 br pr44d l11c_d0 complement af4 br pr44c vref l11t_d0 true ah1 br pr46d pll_ck4c l10c_a0 complement ah2 br pr46c pll_ck4t l10t_a0 true ah3 br v dd io ag4 br v dd 33 ah5 br v dd 33 aj4 br pb47d pll_ck5c l9c_a0 complement ak4 br pb47c pll_ck5t l9t_a0 true al4 br pb46d vref l8c_d2 complement ah6 br pb46c l8t_d2 true aj5 br pb45d l7c_a0 complement ak5 br pb45c l7t_a0 true al5 br pb44d vref l6c_d1 complement aj6 br pb44c l6t_d1 true pin information (continued) table 45. or4e6 432-pin ebga (continued) * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball.
lucent technologies inc. 95 preliminary data sheet august 2000 orca series 4 fpgas ball bank pad function pair* differential ak6 br pb43a al6 br pb42c ah8 br pb41d l5c_d0 complement aj7 br pb41c l5t_d0 true ak7 br pb40d vref l4c_a0 complement al7 br pb40c l4t_a0 true ah9 br v dd io aj8 br pb39d l3c_a0 complement ak8 br pb39c l3t_a0 true aj9 br pb38d l2c_d0 complement ah10 br pb38c vref l2t_d0 true ak9 br pb37d l1c_a0 complement al9 br pb37c l1t_a0 true aj10 bc pb35d vref l13c_a0 complement ak10 bc pb35c l13t_a0 true al10 bc pb34d l12c_d1 complement aj11 bc pb34c l12t_d1 true ah12 bc pb32d vref l11c_d1 complement ak11 bc pb32c l11t_d1 true al11 bc pb31d l10c_d1 complement aj12 bc pb31c l10t_d1 true ah13 bc pb30d vref l9c_d1 complement ak12 bc pb30c l9t_d1 true aj13 bc v dd io ak13 bc pb29d l8c_a0 complement ah14 bc pb29c l8t_a0 true al13 bc pb28d pbck1c l7c_d1 complement aj14 bc pb28c pbck1t l7t_d1 true ak14 bc pb27d l6c_a0 complement al14 bc pb27c l6t_a0 true aj15 bc pb26d vref l5c_a0 complement ak15 bc pb26c l5t_a0 true pin information (continued) table 45. or4e6 432-pin ebga (continued) * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball.
96 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas ball bank pad function pair* differential al15 bc pb24d l4c_d0 complement ak16 bc pb24c vref l4t_d0 true ah16 bc v dd io aj16 bc pb23d pbck0c l3c_d1 complement al17 bc pb23c pbck0t l3t_d1 true ak17 bc pb22d l2c_a0 complement aj17 bc pb22c vref l2t_a0 true al18 bc pb21d l1c_a0 complement ak18 bc pb21c l1t_a0 true aj18 bl pb20d d31 l23c_d1 complement al19 bl pb20c vref l23t_d1 true ah18 bl pb19d d30 l22c_d1 complement ak19 bl pb19c d29 l22t_d1 true aj19 bl pb18d d28 l21c_d0 complement ak20 bl pb18c vref l21t_d0 true ah19 bl v dd io aj20 bl pb17d al21 bl pb16d d27 l20c_a0 complement ak21 bl pb16c d26 l20t_a0 true ah20 bl pb14d d25 l19c_d0 complement aj21 bl pb14c vref l19t_d0 true al22 bl pb13d d24 l18c_a0 complement ak22 bl pb13c d23 l18t_a0 true aj22 bl pb12d d22 l17c_d1 complement al23 bl pb12c vref l17t_d1 true ak23 bl pb11d d21 l16c_d1 complement ah22 bl pb11c d20 l16t_d1 true aj23 bl pb10d d19 l15c_d0 complement ak24 bl pb10c vref l15t_d0 true aj24 bl pb9d d18 l14c_d0 complement ah23 bl pb9c d17 l14t_d0 true al25 bl pb8d d16 l13c_a0 complement pin information (continued) table 45. or4e6 432-pin ebga (continued) * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball.
lucent technologies inc. 97 preliminary data sheet august 2000 orca series 4 fpgas ball bank pad function pair* differential ak25 bl pb8c d15 l13t_a0 true aj25 bl v dd io ah24 bl pb7d l12c_d2 complement al26 bl pb7c l12t_d2 true ak26 bl pb6d d14 l11c_a0 complement aj26 bl pb6c vref l11t_a0 true al27 bl pb5d l10c_a0 complement ak27 bl pb5c l10t_a0 true aj27 bl pb4d dp3 l9c_d0 complement ah26 bl pb4c vref l9t_d0 true al28 bl pb2d pll_ck6c l8c_a0 complement ak28 bl pb2c pll_ck6t l8t_a0 true aj28 bl pb2a dp2 ah27 bl v dd 33 ag28 bl v dd 33 ah29 bl lvds_r lvds_r ah30 bl v dd io ah31 bl ptemp ptemp af28 bl pl47c pll_ck7t l7t_d1 true ag29 bl pl47d pll_ck7c l7c_d1 complement ag30 bl pl45c vref l6t_a0 true ag31 bl pl45d l6c_a0 complement af29 bl pl44c d13 l5t_a0 true af30 bl pl44d vref l5c_a0 complement af31 bl pl42c d12 l4t_d2 true ad28 bl pl42d d11 l4c_d2 complement ae29 bl v dd io ae30 bl pl40c vref l3t_a0 true ae31 bl pl40d l3c_a0 complement ac28 bl pl39c d10 l2t_d0 true ad29 bl pl39d d9 l2c_d0 complement ad30 bl pl38c vref l1t_d0 true pin information (continued) table 45.or4e6 432-pin ebga (continued) * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball.
98 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas ball bank pad function pair* differential ac29 bl pl38d d8 l1c_d0 complement ab28 cl pl37c dp1 l18t_d1 true ac30 cl pl37d dp0 l18c_d1 complement ac31 cl pl36c a0 l17t_d1 true ab29 cl pl36d a1 l17c_d1 complement ab30 cl pl35c a2 l16t_a0 true ab31 cl pl35d a3 l16c_a0 complement aa29 cl pl34c vref l15t_d0 true y28 cl pl34d a4 l15c_d0 complement aa30 cl pl32c vref l14t_a0 true aa31 cl pl32d wr /mpi_rw l14c_a0 complement y29 cl pl31d w28 cl v dd io y30 cl pl30c a5 l13t_d0 true w29 cl pl30d a6 l13c_d0 complement w30 cl pl29c a7 l12t_d1 true v28 cl pl29d vref l12c_d1 complement w31 cl pl28c plck1t/sckb l11t_d1 true v29 cl pl28d plck1c l11c_d1 complement v30 cl pl26c vref l10t_a0 true v31 cl pl26d a8 l10c_a0 complement u29 cl pl25c a9 l9t_a0 true u30 cl pl25d a10 l9c_a0 complement u31 cl v dd io t30 cl pl24c plck0t/scka l8t_a1 true t28 cl pl24d plck0c l8c_a1 complement t29 cl pl23c vref l7t_d1 true r31 cl pl23d rd /mpi_strb l7c_d1 complement r30 cl pl21c vref l6t_a0 true r29 cl pl21d a11 l6c_a0 complement p31 cl pl20c l5t_a0 true p30 cl pl20d l5c_a0 complement pin information (continued) table 45. or4e6 432-pin ebga (continued) * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball.
lucent technologies inc. 99 preliminary data sheet august 2000 orca series 4 fpgas ball bank pad function pair* differential p29 cl pl19c a12 l4t_d1 true n31 cl pl19d a13 l4c_d1 complement p28 cl v dd io n30 cl pl18c vref l3t_a0 true n29 cl pl18d rdy/busy /rclk l3c_a0 complement m30 cl pl17d n28 cl pl16c d4 l2t_d0 true m29 cl pl16d vref l2c_d0 complement l31 cl pl14c a14 l1t_a0 true l30 cl pl14d a15 l1c_a0 complement m28 tl pl13c a16 l24t_d0 true l29 tl pl13d vref l24c_d0 complement k31 tl pl12c dout l23t_a0 true k30 tl pl12d init l23c_a0 complement k29 tl pl11c l22t_d1 true j31 tl pl11d l22c_d1 complement j30 tl pl10c cs1 l21t_d1 true k28 tl pl10d cs0 l21c_d1 complement j29 tl pl9c a17 l20t_d0 true h30 tl pl9d vref l20c_d0 complement h29 tl v dd io j28 tl pl8c d7 l19t_d2 true g31 tl pl8d l19c_d2 complement g30 tl pl6c ldc l18t_a0 true g29 tl pl6d hdc l18c_a0 complement h28 tl pl4c d6 l17t_d2 true f31 tl pl4d d5 l17c_d2 complement f30 tl pl3c vref l16t_a0 true f29 tl pl3d l16c_a0 complement e31 tl pl2c pll_ck0t l15t_a0 true e30 tl pl2d pll_ck0c l15c_a0 complement e29 tl v dd io pin information (continued) table 45. or4e6 432-pin ebga (continued) * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball.
100 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas ball bank pad function pair* differential f28 tl pprgrm prgrm d31 tl prd_cfg rd_cfg d30 tl preset reset d29 tl prd_data rd_data/tdo e28 tl v dd 33 d27 tl v dd 33 c28 tl pdone done b28 tl pcclk cclk a28 tl pcfg_mpi_irq cfg_irq /mpi_irq d26 tl pt2c pll_ck1t l14t_d0 true c27 tl pt2d pll_ck1c l14c_d0 complement b27 tl pt3c vref l13t_a0 true a27 tl pt3d l13c_a0 complement c26 tl pt4c tck l12t_a0 true b26 tl pt4d tdi l12c_a0 complement a26 tl pt6c d2 l11t_d2 true d24 tl pt6d d1 l11c_d2 complement c25 tl v dd io b25 tl pt8c d3 l10t_a0 true a25 tl pt8d a18/mpi_tsz0 l10c_a0 complement d23 tl pt9c a19/mpi_tsz1 l9t_d0 true c24 tl pt9d a20/mpi_bdip l9c_d0 complement b24 tl pt10c tms l8t_d0 true c23 tl pt10d d0 l8c_d0 complement d22 tl pt11c l7t_d1 true b23 tl pt11d vref l7c_d1 complement a23 tl pt13c mpi_tea l6t_d1 true c22 tl pt13d vref l6c_d1 complement b22 tl pt14c m3 l5t_a0 true a22 tl pt14d m2 l5c_a0 complement c21 tl pt15c a21/mpi_burst l4t_d0 true d20 tl pt15d mpi_clk l4c_d0 complement pin information (continued) table 45. or4e6 432-pin ebga (continued) * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball.
lucent technologies inc. 101 preliminary data sheet august 2000 orca series 4 fpgas ball bank pad function pair* differential b21 tl pt16c m1 l3t_a0 true a21 tl pt16d m0 l3c_a0 complement c20 tl pt17c vref l2t_d0 true d19 tl pt17d l2c_d0 complement b20 tl v dd io c19 tl pt18c mpi_ack l1t_a0 true b19 tl pt18d mpi_rtry l1c_a0 complement d18 tc pt19c vref l15t_d2 true a19 tc pt19d l15c_d2 complement c18 tc pt20c l14t_a0 true b18 tc pt20d l14c_a0 complement a18 tc pt21c l13t_d1 true c17 tc pt21d vref l13c_d1 complement b17 tc pt22c ptck0t l12t_a0 true a17 tc pt22d ptck0c l12c_a0 complement b16 tc pt23c ptck1t l11t_a1 true d16 tc pt23d ptck1c l11c_a1 complement c16 tc v dd io a15 tc pt24c vref l10t_a0 true b15 tc pt24d l10c_a0 complement c15 tc pt26c l9t_d1 true a14 tc pt26d l9c_d1 complement b14 tc pt28c l8t_a0 true c14 tc pt28d l8c_a0 complement a13 tc pt29c vref l7t_d2 true d14 tc pt29d l7c_d2 complement b13 tc v dd io c13 tc pt30c l6t_d0 true b12 tc pt30d l6c_d0 complement d13 tc pt31c l5t_d0 true c12 tc pt31d l5c_d0 complement a11 tc pt32c vref l4t_a0 true pin information (continued) table 45. or4e6 432-pin ebga (continued) * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball.
102 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas ball bank pad function pair* differential b11 tc pt32d l4c_a0 complement d12 tc pt33c l3t_d0 true c11 tc pt33d l3c_d0 complement a10 tc pt34c l2t_a0 true b10 tc pt34d vref l2c_a0 complement c10 tc pt35c l1t_d1 true a9 tc pt35d l1c_d1 complement b9 tr pt36c l19t_d1 true d10 tr pt36d l19c_d1 complement c9 tr pt38c vref l18t_d0 true b8 tr pt38d l18c_d0 complement c8 tr pt39c l17t_d0 true d9 tr pt39d l17c_d0 complement a7 tr v dd io b7 tr pt40c vref l16t_a0 true c7 tr pt40d l16c_a0 complement d8 tr pt41c l15t_d2 true a6 tr pt41d l15c_d2 complement b6 tr pt42c l14t_a0 true c6 tr pt42d vref l14c_a0 complement a5 tr pt43c l13t_a0 true b5 tr pt43d l13c_a0 complement c5 tr pt45c l12t_d0 true d6 tr pt45d vref l12c_d0 complement a4 tr pt47c pll_ck2t l11t_a0 true b4 tr pt47d pll_ck2c l11c_a0 complement c4 tr pll_vf pll_vf d5 tr v dd 33 a12 tl v ss a16 tl v ss a2 tl v ss a20 tl v ss pin information (continued) table 45. or4e6 432-pin ebga (continued) * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball.
lucent technologies inc. 103 preliminary data sheet august 2000 orca series 4 fpgas ball bank pad function pair* differential a24 tl v ss a29 tl v ss a3 cl v ss a30 cl v ss a8 cl v ss ad1 cl v ss ad31 cl v ss aj1 bl v ss aj2 bl v ss aj30 bl v ss aj31 bl v ss ak1 bl v ss ak29 bl v ss ak3 bc v ss ak31 bc v ss al12 bc v ss al16 bc v ss al2 bc v ss al20 br v ss al24 br v ss al29 br v ss al3 br v ss al30 br v ss al8 br v ss b1 cr v ss b29 cr v ss b3 cr v ss b31 cr v ss c1 cr v ss c2 tr v ss c30 tr v ss c31 tr v ss pin information (continued) table 45. or4e6 432-pin ebga (continued) * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball.
104 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas ball bank pad function pair* differential h1 tr v ss h31 tr v ss m1 tr v ss m31 tc v ss t1 tc v ss t31 tc v ss y1 tc v ss y31 tc v ss a1 tl v dd 15 a31 tl v dd 15 aa28 tl v dd 15 aa4 tl v dd 15 ae28 tl v dd 15 ae4 cl v dd 15 ah11 cl v dd 15 ah15 cl v dd 15 ah17 cl v dd 15 ah21 cl v dd 15 ah25 bl v dd 15 ah28 bl v dd 15 ah4 bl v dd 15 ah7 bl v dd 15 aj29 bl v dd 15 aj3 bc v dd 15 ak2 bc v dd 15 ak30 bc v dd 15 al1 bc v dd 15 al31 bc v dd 15 b2 br v dd 15 b30 br v dd 15 c29 br v dd 15 c3 br v dd 15 pin information (continued) table 45. or4e6 432-pin ebga (continued) * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball.
lucent technologies inc. 105 preliminary data sheet august 2000 orca series 4 fpgas ball bank pad function pair* differential d11 br v dd 15 d15 cr v dd 15 d17 cr v dd 15 d21 cr v dd 15 d25 cr v dd 15 d28 cr v dd 15 d4 tr v dd 15 d7 tr v dd 15 g28 tr v dd 15 g4 tr v dd 15 l28 tr v dd 15 l4 tc v dd 15 r28 tc v dd 15 r4 tc v dd 15 r4 tc v dd 15 u28 tc v dd 15 pin information (continued) table 45. or4e6 432-pin ebga (continued) * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball.
106 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas pin information (continued) table 46. or4e6 680-pin pbgam pinout ball bank pad function pair* differential f5 tl v dd 33 e4 tl prd_data rd_data/tdo e3 tl preset reset d2 tl prd_cfg rd_cfg g5 tl pprgrm prgrm d1 tl pl2d pll_ck0c l21c_d2 complement f4 tl pl2c pll_ck0t l21t_d2 true f3 tl pl3d l22c_d0 complement g4 tl pl3c vref l22t_d0 true e2 tl pl4d d5 l23c_d2 complement h5 tl pl4c d6 l23t_d2 true e1 tl pl5d l24c_d0 complement f2 tl pl5c vref l24t_d0 true j5 tl pl6d hdc l25c_d3 complement f1 tl pl6c ldc l25t_d3 true h4 tl pl7d l26c_d0 complement g3 tl pl7c l26t_d0 true h3 tl pl8d l27c_d0 complement g2 tl pl8c d7 l27t_d0 true k5 tl pl9d vref l28c_d3 complement g1 tl pl9c a17 l28t_d3 true j4 tl pl10d cs0 l29c_d1 complement l5 tl pl10c cs1 l29t_d1 true j3 tl pl11d l30c_d0 complement h2 tl pl11c l30t_d0 true k4 tl pl11a h1 tl pl12d init l31c_d0 complement j2 tl pl12c dout l31t_d0 true j1 tl pl13d vref l32c_d1 complement k3 tl pl13c a16 l32t_d1 true m5 tl pl13a l4 cl pl14d a15 l1c_d1 complement * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball.
lucent technologies inc. 107 preliminary data sheet august 2000 orca series 4 fpgas ball bank pad function pair* differential k2 cl pl14c a14 l1t_d1 true k1 cl pl15d l2c_d0 complement l2 cl pl15c l2t_d0 true l3 cl pl16d vref l3c_d1 complement n5 cl pl16c d4 l3t_d1 true m4 cl pl17d l4c_a1 complement m2 cl pl17c l4t_a1 true p5 cl pl18d rdy/busy /rclk l5c_d3 complement m1 cl pl18c vref l5t_d3 true n1 cl pl19d a13 l6c_a2 complement n4 cl pl19c a12 l6t_a2 true n2 cl pl20d l7c_d0 complement p1 cl pl20c l7t_d0 true r5 cl pl20a p2 cl pl21d a11 l8c_a0 complement p3 cl pl21c vref l8t_a0 true t5 cl pl21a p4 cl pl22d l9c_d2 complement r1 cl pl22c l9t_d2 true r2 cl pl22a l10t_a1 true r4 cl pl22b l10c_a1 complement u5 cl pl23d rd /mpi_strb l11c_d0 complement t4 cl pl23c vref l11t_d0 true t1 cl pl23a l12t_d3 true v5 cl pl23b l12c_d3 complement t2 cl pl24d plck0c l13c_a0 complement t3 cl pl24c plck0t/scka l13t_a0 true u4 cl pl24b l14c_a0 complement u3 cl pl24a l14t_a0 true u2 cl pl25d a10 l15c_a0 complement v2 cl pl25c a9 l15t_a0 true v3 cl pl25b l16c_a0 complement pin information (continued) table 46. or4e6 680-pin pbgam pinout (continued) * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball.
108 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas ball bank pad function pair* differential v4 cl pl25a l16t_a0 true w5 cl pl26d a8 l17c_a2 complement w2 cl pl26c vref l17t_a2 true w3 cl pl27d l18c_d1 complement y1 cl pl27c l18t_d1 true y2 cl pl27a w4 cl pl28d plck1c l19c_d2 complement aa1 cl pl28c plck1t/sckb l19t_d2 true aa2 cl pl28a y5 cl pl29d vref l20c_a0 complement y4 cl pl29c a7 l20t_a0 true aa3 cl pl29a aa5 cl pl30d a6 l21c_d3 complement ab1 cl pl30c a5 l21t_d3 true ab2 cl pl31d aa4 cl pl32d wr /mpi_rw l22c_a0 complement ab4 cl pl32c vref l22t_a0 true ab5 cl pl33d l23c_d3 complement ac1 cl pl33c l23t_d3 true ac2 cl pl34d a4 l23c_a2 complement ac5 cl pl34c vref l23t_a2 true ad2 cl pl35d a3 l23c_a0 complement ad3 cl pl35c a2 l23t_a0 true ac4 cl pl35a ae1 cl pl36d a1 l24c_a0 complement ae2 cl pl36c a0 l24t_a0 true ad4 cl pl37d dp0 l25c_d0 complement ae3 cl pl37c dp1 l25t_d0 true ad5 cl pl37a af1 bl pl38d d8 l1c_a0 complement af2 bl pl38c vref l1t_a0 true ae4 bl pl38a pin information (continued) table 46. or4e6 680-pin pbgam pinout (continued) * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball.
lucent technologies inc. 109 preliminary data sheet august 2000 orca series 4 fpgas ball bank pad function pair* differential af3 bl pl39d d9 l2c_a0 complement af4 bl pl39c d10 l2t_a0 true ae5 bl pl40d l3c_d3 complement ag1 bl pl40c vref l3t_d3 true ag2 bl pl41d l4c_d2 complement af5 bl pl41c l4t_d2 true ag3 bl pl42d d11 l5c_a0 complement ag4 bl pl42c d12 l5t_a0 true ah1 bl pl43d l6c_a1 complement ah3 bl pl43c l6t_a1 true ah4 bl pl44d vref l7c_d0 complement ag5 bl pl44c d13 l7t_d0 true ah2 bl pl44b aj2 bl pl45d l8c_d2 complement ah5 bl pl45c vref l8t_d2 true aj3 bl pl45a aj4 bl pl46d aj1 bl pl46a ak1 bl pl47d pll_ck7c l9c_a0 complement ak2 bl pl47c pll_ck7t l9t_a0 true aj5 bl pl47b l10c_d1 complement ak3 bl pl47a l10t_d1 true ak4 bl ptemp ptemp al1 bl lvds_r lvds_r al2 bl v dd 33 ak6 bl v dd 33 al5 bl pb2a dp2 l11t_a0 true am5 bl pb2b l11c_a0 complement an4 bl pb2c pll_ck6t l12t_d2 true ak7 bl pb2d pll_ck6c l12c_d2 complement ap4 bl pb3a al6 bl pb3c l13t_a0 true pin information (continued) table 46. or4e6 680-pin pbgam pinout (continued) * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball.
110 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas ball bank pad function pair* differential am6 bl pb3d l13c_a0 complement al7 bl pb4c vref l14t_d1 true an5 bl pb4d dp3 l14c_d1 complement ak8 bl pb5c l15t_d3 true ap5 bl pb5d l15c_d3 complement an6 bl pb6c vref l16t_d2 true ak9 bl pb6d d14 l16c_d2 complement ap6 bl pb7c l17t_d2 true al8 bl pb7d l17c_d2 complement am7 bl pb8c d15 l18t_a0 true am8 bl pb8d d16 l18c_a0 complement an7 bl pb9a ak10 bl pb9c d17 l19t_d3 true ap7 bl pb9d d18 l19c_d3 complement al9 bl pb10a ak11 bl pb10c vref l20t_d1 true am9 bl pb10d d19 l20c_d1 complement an8 bl pb11a al10 bl pb11c d20 l21t_d2 true ap8 bl pb11d d21 l21c_d2 complement an9 bl pb12a ap9 bl pb12c vref l22t_d1 true am10 bl pb12d d22 l22c_d1 complement ak12 bl pb13a l23t_d0 true al11 bl pb13b l23c_d0 complement an10 bl pb13c d23 l24t_a0 true ap10 bl pb13d d24 l24c_a0 complement an11 bl pb14a l25t_a0 true am11 bl pb14b l25c_a0 complement ak13 bl pb14c vref l26t_d0 true al12 bl pb14d d25 l26c_d0 complement an12 bl pb15c l27t_d2 true pin information (continued) table 46. or4e6 680-pin pbgam pinout (continued) * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball.
lucent technologies inc. 111 preliminary data sheet august 2000 orca series 4 fpgas ball bank pad function pair* differential ak14 bl pb15d l27c_d2 complement ap12 bl pb16c d26 l28t_a0 true ap13 bl pb16d d27 l28c_a0 complement al13 bl pb17c l29t_a1 true an13 bl pb17d l29c_a1 complement ap14 bl pb18c vref l30t_d3 true ak15 bl pb18d d28 l30c_d3 complement an14 bl pb19a am14 bl pb19c d29 l31t_d1 true ak16 bl pb19d d30 l31c_d1 complement al14 bl pb20a ap15 bl pb20c vref l32t_a2 true al15 bl pb20d d31 l32c_a2 complement an15 bc pb21a an16 bc pb21c l1t_d2 true ak17 bc pb21d l1c_d2 complement al16 bc pb22a am16 bc pb22c vref l2t_a1 true ap16 bc pb22d l2c_a1 complement an17 bc pb23a l3t_a1 true al17 bc pb23b l3c_a1 complement am17 bc pb23c pbck0t l4t_a0 true am18 bc pb23d pbck0c l4c_a0 complement an18 bc pb24b l5c_a1 complement al18 bc pb24a l5t_a1 true al19 bc pb24c vref l6t_d0 true ak18 bc pb24d l6c_d0 complement am19 bc pb25c l7t_a0 true an19 bc pb25d l7c_a0 complement ap20 bc pb26c l8t_a0 true an20 bc pb26d vref l8c_a0 complement al20 bc pb27a pin information (continued) table 46. or4e6 680-pin pbgam pinout (continued) * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball.
112 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas ball bank pad function pair* differential ap21 bc pb27c l9t_a0 true an21 bc pb27d l9c_a0 complement ak19 bc pb28a am21 bc pb28c pbck1t l10t_a0 true al21 bc pb28d pbck1c l10c_a0 complement ak20 bc pb29a ap22 bc pb29c l11t_a0 true an22 bc pb29d l11c_a0 complement ak21 bc pb30a al22 bc pb30c l12t_a0 true al23 bc pb30d vref l12c_a0 complement ak22 bc pb31c l13t_d2 true an23 bc pb31d l13c_d2 complement ap23 bc pb32c l14t_a3 true ak23 bc pb32d vref l14c_a3 complement an24 bc pb33c l15t_a0 true am24 bc pb33d l15c_a0 complement al24 bc pb34c l16t_d2 true ap25 bc pb34d l16t_d2 complement an25 bc pb35a ak24 bc pb35c l17t_d3 true ap26 bc pb35d vref l17c_d3 complement an26 bc pb36a al25 bc pb36c l18t_a0 true am25 bc pb36d l18c_a0 complement am26 br pb37a ap27 br pb37c l1t_a0 true an27 br pb37d l1c_a0 complement ak25 br pb38c vref l2t_d0 true al26 br pb38d l2c_d0 complement am27 br pb39c l3t_d1 true ak26 br pb39d l3c_d1 complement pin information (continued) table 46. or4e6 680-pin pbgam pinout (continued) * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball.
lucent technologies inc. 113 preliminary data sheet august 2000 orca series 4 fpgas ball bank pad function pair* differential ap28 br pb40c l4t_a0 true an28 br pb40d vref l4c_a0 complement al27 br pb41c l5t_a0 true al28 br pb41d l5c_a0 complement ak27 br pb42c am28 br pb43a an29 br pb43d ak28 br pb44c l6t_d1 true am29 br pb44d vref l6c_d1 complement ap29 br pb45b l7c_a2 complement al29 br pb45a l7t_a2 true ap30 br pb45c l8t_a0 true an30 br pb45d l8c_a0 complement ak29 br pb46c l9t_d1 true am30 br pb46d vref l9c_d1 complement al30 br pb47c pll_ck5t l10t_d2 true ap31 br pb47d pll_ck5c l10c_d2 complement an31 br v dd 33 ak31 br v dd 33 aj30 br pr46c pll_ck4t l11t_d1 true ak32 br pr46d pll_ck4c l11c_d1 complement al33 br pr45c l12t_d2 true ah30 br pr45d l12c_d2 complement al34 br pr44c vref l13t_d2 true aj31 br pr44d l13c_d2 complement aj32 br pr43c l14t_d0 true ah31 br pr43d l14c_d0 complement ak33 br pr42c l15t_d2 true ag30 br pr42d l15c_d2 complement ak34 br pr41c vref l16t_d0 true aj33 br pr41d l16c_d0 complement af30 br pr40a pin information (continued) table 46. or4e6 680-pin pbgam pinout (continued) * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball.
114 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas ball bank pad function pair* differential aj34 br pr40c l17t_d2 true ag31 br pr40d l17c_d2 complement ah32 br pr39a ag32 br pr39c l18t_d0 true ah33 br pr39d vref l18c_d0 complement ae30 br pr38a ah34 br pr38c l19t_d2 true af31 br pr38d l19c_d2 complement af32 br pr37a ag33 br pr37c l20t_d1 true ae31 br pr37d vref l20c_d1 complement ag34 br pr36a af33 br pr36b ad30 br pr36c l21t_d3 true af34 br pr36d l21c_d3 complement ae32 cr pr35c l1t_d1 true ac30 cr pr35d l1c_d1 complement ad31 cr pr34a ae33 cr pr34c l2t_d1 true ac31 cr pr34d l2c_d1 complement ae34 cr pr33b ad32 cr pr33c vref l3t_d1 true ab30 cr pr33d l3c_d1 complement ad33 cr pr32b ab31 cr pr32c l4t_d0 true aa30 cr pr32d l4c_d0 complement aa31 cr pr31a ac33 cr pr31c l5t_a0 true ab33 cr pr31d vref l5c_a0 complement ac34 cr pr30a aa32 cr pr30c l6t_d1 true y30 cr pr30d l6c_d1 complement pin information (continued) table 46. or4e6 680-pin pbgam pinout (continued) * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball.
lucent technologies inc. 115 preliminary data sheet august 2000 orca series 4 fpgas ball bank pad function pair* differential y31 cr pr29b ab34 cr pr29c l7t_d3 true w30 cr pr29d vref l7c_d3 complement aa34 cr pr28a aa33 cr pr28c l8t_d1 true w31 cr pr28d l8c_d1 complement y33 cr pr27a y34 cr pr27c prck1t l9t_d0 true w33 cr pr27d prck1c l9c_d0 complement w32 cr pr26a v30 cr pr26c l10t_a0 true v31 cr pr26d vref l10c_a0 complement v33 cr pr25c l11t_a0 true v32 cr pr25d l11c_a0 complement u33 cr pr24a l12t_a0 true u32 cr pr24b l12c_a0 complement t34 cr pr24c prck0t l13t_d2 true u31 cr pr24d prck0c l13c_d2 complement t33 cr pr23a t32 cr pr23c vref l14t_a0 true t31 cr pr23d l14c_a0 complement u30 cr pr22a r31 cr pr22c l15t_d1 true r34 cr pr22d l15c_d1 complement r33 cr pr21a p34 cr pr21c l16t_a1 true p32 cr pr21d vref l16c_a1 complement t30 cr pr20a p31 cr pr20c l17t_a1 true p33 cr pr20d l17c_a1 complement r30 cr pr19b n33 cr pr19c l18t_a1 true pin information (continued) table 46. or4e6 680-pin pbgam pinout (continued) * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball.
116 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas ball bank pad function pair* differential n31 cr pr19d l18c_a1 complement n34 cr pr18b m31 cr pr18c l19t_a1 true m33 cr pr18d l19c_a1 complement p30 cr pr17a m34 cr pr17c vref l20t_d1 true l32 cr pr17d l20c_d1 complement l31 cr pr16d l33 cr pr15a k34 cr pr15c l21t_a0 true k33 cr pr15d l21c_a0 complement k32 cr pr14a n30 cr pr14c vref l22t_d2 true k31 cr pr14d l22c_d2 complement j34 tr pr13b l1c_a0 complement h34 tr pr13a l1t_a0 true j33 tr pr13c l2t_a1 true j31 tr pr13d vref l2c_a1 complement j32 tr pr12c l3t_d1 true g34 tr pr12d l3c_d1 complement m30 tr pr11a h33 tr pr11c l4t_a0 true h32 tr pr11d l4c_a0 complement l30 tr pr10a h31 tr pr10c l5t_d1 true g33 tr pr10d l5c_d1 complement f34 tr pr9a f33 tr pr9c vref l6t_d0 true g32 tr pr9d l6c_d0 complement k30 tr pr8c l7t_d2 true g31 tr pr8d l7c_d2 complement e34 tr pr7c l8t_d2 true pin information (continued) table 46. or4e6 680-pin pbgam pinout (continued) * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball.
lucent technologies inc. 117 preliminary data sheet august 2000 orca series 4 fpgas ball bank pad function pair* differential j30 tr pr7d vref l8c_d2 complement d34 tr pr6a f32 tr pr6c l9t_a0 true f31 tr pr6d l9c_a0 complement e33 tr pr5c l10t_a0 true d33 tr pr5d l10c_a0 complement h30 tr pr4c l11t_d2 true e32 tr pr4d vref l11c_d2 complement e31 tr pr3c pll_ck3t l12t_a0 true g30 tr pr3d pll_ck3c l12c_a0 complement f30 tr v dd 33 e29 tr v dd 33 d30 tr pll_vf pll_vf c30 tr pt47d pll_ck2c l13c_d0 complement b31 tr pt47c pll_ck2t l13t_d0 true e28 tr pt46d l14c_d2 complement b30 tr pt46c l14t_d2 true d29 tr pt45d vref l15c_d2 complement a31 tr pt45c l15t_d2 true d28 tr pt44d l16c_d1 complement b29 tr pt44c l16t_d1 true e27 tr pt43d l17c_d1 complement c29 tr pt43c l17t_d1 true a30 tr pt42d vref l18c_d3 complement e26 tr pt42c l18t_d3 true a29 tr pt41d l19c_d2 complement d27 tr pt41c l19t_d2 true c28 tr pt40d l20c_a0 complement c27 tr pt40c vref l20t_a0 true b28 tr pt39d l21c_d2 complement e25 tr pt39c l21t_d2 true a28 tr pt38d l22c_d2 complement pin information (continued) table 46. or4e6 680-pin pbgam pinout (continued) * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball.
118 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas ball bank pad function pair* differential d26 tr pt38c vref l22t_d2 true c26 tr pt37d b27 tr pt37a d25 tr pt36d l23c_d2 complement a27 tr pt36c l23t_d2 true a26 tr pt36a l24t_a0 true b26 tr pt36b l24c_a0 complement c25 tc pt35d l1c_d1 complement e24 tc pt35c l1t_d1 true d24 tc pt35a l2t_d2 true a25 tc pt35b l2c_d2 complement d23 tc pt34d vref l3c_d1 complement b25 tc pt34c l3t_d1 true c24 tc pt33d l4c_d1 complement e23 tc pt33c l4t_d1 true b24 tc pt32d l5c_d1 complement d22 tc pt32c vref l5t_d1 true e22 tc pt31d l6c_d0 complement d21 tc pt31c l6t_d0 true b23 tc pt30d l7c_a0 complement b22 tc pt30c l7t_a0 true a23 tc pt29d l8c_d1 complement c21 tc pt29c vref l8t_d1 true e21 tc pt29a d20 tc pt28d l9c_d2 complement a22 tc pt28c l9t_d2 true e20 tc pt28a a21 tc pt27d l10c_a0 complement b21 tc pt27c l10t_a0 true d19 tc pt27a b20 tc pt26d l11c_a0 complement a20 tc pt26c l11t_a0 true pin information (continued) table 46. or4e6 680-pin pbgam pinout (continued) * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball.
lucent technologies inc. 119 preliminary data sheet august 2000 orca series 4 fpgas ball bank pad function pair* differential b19 tc pt25d l12c_a0 complement c19 tc pt25c l12t_a0 true e19 tc pt24d l13c_d0 complement d18 tc pt24c vref l13t_d0 true b18 tc pt24a l14t_a0 true c18 tc pt24b l14c_a0 complement b17 tc pt23d ptck1c l15c_d0 complement c17 tc pt23c ptck1t l15t_d0 true d17 tc pt23a l16t_d2 true a16 tc pt23b l16c_d2 complement b16 tc pt22d ptck0c l17c_a0 complement c16 tc pt22c ptck0t l17t_a0 true d16 tc pt22a e18 tc pt21d vref l18c_d3 complement a15 tc pt21c l18t_d3 true b15 tc pt21a d15 tc pt20d l19c_d2 complement a14 tc pt20c l19t_d2 true b14 tc pt20a e17 tc pt19d l20c_d3 complement a13 tc pt19c vref l20t_d3 true b13 tc pt19a e16 tl pt18d mpi_rtry l1c_d1 complement d14 tl pt18c mpi_ack l1t_d1 true c14 tl pt17d l2c_d0 complement d13 tl pt17c vref l2t_d0 true a12 tl pt16d m0 l3c_a0 complement b12 tl pt16c m1 l3t_a0 true e15 tl pt15d mpi_clk l4c_d3 complement b11 tl pt15c a21/mpi_burst l4t_d3 true c11 tl pt14d m2 l5c_d2 complement e14 tl pt14c m3 l5t_d2 true pin information (continued) table 46. or4e6 680-pin pbgam pinout (continued) * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball.
120 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas ball bank pad function pair* differential d12 tl pt13d vref l6c_a0 complement d11 tl pt13c mpi_tea l6t_a0 true a10 tl pt12d l7c_a0 complement b10 tl pt12c l7t_a0 true c10 tl pt12a c9 tl pt11d vref l8c_d0 complement d10 tl pt11c l8t_d0 true e13 tl pt11a b9 tl pt10d d0 l9c_a0 complement a9 tl pt10c tms l9t_a0 true d9 tl pt9d a20/mpi_bdip l10c_d2 complement a8 tl pt9c a19/mpi_tsz1 l10t_d2 true b8 tl pt8d a18/mpi_tsz0 l11c_d3 complement e12 tl pt8c d3 l11t_d3 true c8 tl pt7d vref l12c_a0 complement d8 tl pt7c l12t_a0 true e11 tl pt6d d1 l13c_d3 complement a7 tl pt6c d2 l13t_d3 true a6 tl pt5d l14c_d0 complement b7 tl pt5c vref l14t_d0 true c7 tl pt4d tdi l15c_a0 complement d7 tl pt4c tck l15t_a0 true e10 tl pt4b l16c_d4 complement a5 tl pt4a l16t_d4 true b6 tl pt3d l17c_d2 complement e9 tl pt3c vref l17t_d2 true a4 tl pt3b l18c_d0 complement b5 tl pt3a l18t_d0 true d6 tl pt2d pll_ck1c l19c_a0 complement c6 tl pt2c pll_ck1t l19t_a0 true c5 tl pt2b l20c_d1 complement e7 tl pcfg_mpi_irq cfg_irq /mpi_irq pin information (continued) table 46. or4e6 680-pin pbgam pinout (continued) * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball.
lucent technologies inc. 121 preliminary data sheet august 2000 orca series 4 fpgas ball bank pad function pair* differential e8 tl pt2a l20t_d1 true e6 tl pcclk cclk b4 tl pdone done d5 tl v dd 33 a1 tl v ss a2 tl v ss a18 tl v ss a33 tl v ss a34 tl v ss b1 tl v ss b2 tl v ss b33 tl v ss b34 tl v ss c3 tl v ss c13 tl v ss c22 tc v ss c32 tc v ss d4 tc v ss d31 tc v ss n3 tc v ss n13 tc v ss n14 tc v ss n15 tc v ss n20 tc v ss n21 tc v ss n22 tc v ss n32 tr v ss p13 tr v ss p14 tr v ss p15 tr v ss p20 tr v ss p21 tr v ss pin information (continued) table 46. or4e6 680-pin pbgam pinout (continued) * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball.
122 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas ball bank pad function pair* differential p22 tr v ss r13 tr v ss r14 tr v ss r15 tr v ss r20 tr v ss r21 cr v ss r22 cr v ss t16 cr v ss t17 cr v ss t18 cr v ss t19 cr v ss u16 cr v ss u17 cr v ss u18 cr v ss u19 cr v ss v1 cr v ss v16 br v ss v17 br v ss v18 br v ss v19 br v ss v34 br v ss w16 br v ss w17 br v ss w18 br v ss w19 br v ss y13 br v ss y14 br v ss y15 bc v ss y20 bc v ss y21 bc v ss y22 bc v ss aa13 bc v ss pin information (continued) table 46. or4e6 680-pin pbgam pinout (continued) * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball.
lucent technologies inc. 123 preliminary data sheet august 2000 orca series 4 fpgas ball bank pad function pair* differential aa14 bc v ss aa15 bc v ss aa20 bc v ss aa21 bc v ss aa22 bc v ss ab3 bc v ss ab13 bl v ss ab14 bl v ss ab15 bl v ss ab20 bl v ss ab21 bl v ss ab22 bl v ss ab32 bl v ss al4 bl v ss al31 bl v ss am3 bl v ss am13 bl v ss am22 cl v ss am32 cl v ss an1 cl v ss an2 cl v ss an33 cl v ss an34 cl v ss ap1 cl v ss ap2 cl v ss ap18 cl v ss ap33 cl v ss ap34 cl v ss n16 tl v dd 15 n17 tl v dd 15 n18 tl v dd 15 n19 tl v dd 15 pin information (continued) table 46. or4e6 680-pin pbgam pinout (continued) * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball.
124 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas ball bank pad function pair* differential p16 tl v dd 15 p17 tl v dd 15 p18 tc v dd 15 p19 tc v dd 15 r16 tc v dd 15 r17 tc v dd 15 r18 tc v dd 15 r19 tc v dd 15 t13 tr v dd 15 t14 tr v dd 15 t15 tr v dd 15 t20 tr v dd 15 t21 tr v dd 15 t22 tr v dd 15 u13 cr v dd 15 u14 cr v dd 15 u15 cr v dd 15 u20 cr v dd 15 u21 cr v dd 15 u22 cr v dd 15 v13 br v dd 15 v14 br v dd 15 v15 br v dd 15 v20 br v dd 15 v21 br v dd 15 v22 br v dd 15 w13 bc v dd 15 w14 bc v dd 15 w15 bc v dd 15 w20 bc v dd 15 w21 bc v dd 15 w22 bc v dd 15 pin information (continued) table 46. or4e6 680-pin pbgam pinout (continued) * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball.
lucent technologies inc. 125 preliminary data sheet august 2000 orca series 4 fpgas ball bank pad function pair* differential y16 bl v dd 15 y17 bl v dd 15 y18 bl v dd 15 y19 bl v dd 15 aa16 bl v dd 15 aa17 bl v dd 15 aa18 cl v dd 15 aa19 cl v dd 15 ab16 cl v dd 15 ab17 cl v dd 15 ab18 cl v dd 15 ab19 cl v dd 15 a3 tl v dd io b3 tl v dd io c1 tl v dd io c2 tl v dd io c4 tl v dd io d3 tl v dd io e5 tl v dd io a11 tc v dd io a17 tc v dd io a19 tc v dd io a24 tc v dd io c12 tc v dd io c15 tc v dd io c20 tc v dd io c23 tc v dd io a32 tr v dd io b32 tr v dd io c31 tr v dd io c33 tr v dd io c34 tr v dd io pin information (continued) table 46. or4e6 680-pin pbgam pinout (continued) * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball.
126 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas ball bank pad function pair* differential d32 tr v dd io e30 tr v dd io l34 cr v dd io m32 cr v dd io r32 cr v dd io u34 cr v dd io w34 cr v dd io y32 cr v dd io ac32 cr v dd io ad34 cr v dd io ak30 br v dd io al32 br v dd io am31 br v dd io am33 br v dd io am34 br v dd io an32 br v dd io ap32 br v dd io am12 bc v dd io am15 bc v dd io am20 bc v dd io am23 bc v dd io ap11 bc v dd io ap17 bc v dd io ap19 bc v dd io ap24 bc v dd io ak5 bl v dd io al3 bl v dd io am1 bl v dd io am2 bl v dd io am4 bl v dd io an3 bl v dd io ap3 bl v dd io pin information (continued) table 46. or4e6 680-pin pbgam pinout (continued) * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball.
lucent technologies inc. 127 preliminary data sheet august 2000 orca series 4 fpgas ball bank pad function pair* differential l1 cl v dd io m3 cl v dd io r3 cl v dd io u1 cl v dd io w1 cl v dd io y3 cl v dd io ac3 cl v dd io ad1 cl v dd io pin information (continued) table 46. or4e6 680-pin pbgam pinout (continued) * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball.
128 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas package outline drawings 352-pin pbga dimensions are in millimeters. 5-4407(f) note: although the 36 thermal enhancement balls are stated as an option, they are standard on the 352 fpga package. 0.56 0.06 1.17 0.05 2.33 0.21 seating plane solder ball 0.60 0.10 0.20 pwb mold compound 35.00 +0.70 C0.00 30.00 a1 ball identifier zone af ae ad ac ab aa y w v u t r g 25 spaces @ 1.27 = 31.75 p n m l k j h 1 2 3 4 5 6 7 8 9 10 12 14 16 18 22 24 26 20 11 13 15 17 21 19 23 25 f e d c b a center array 25 spaces a1 ball 0.75 0.15 35.00 0.20 30.00 +0.70 C0.00 0.20 @ 1.27 = 31.75 for thermal enhancement (optional) corner (see note below)
lucent technologies inc. 129 preliminary data sheet august 2000 orca series 4 fpgas package outline drawings (continued) 432-pin ebga dimensions are in millimeters. 5-4409(f) 0.91 0.06 1.54 0.13 seating plane solder ball 0.63 0.07 0.20 40.00 0.10 40.00 a1 ball m d ag b f k h g e ad l t j n aj c y p ah ae ac aa w u r ak af ab v al a 19 30 26 5 28 24 22 23 25 7 20 31 29 15 21 18 327 11 17 4 6 810121416 2 913 1 30 spaces @ 1.27 = 38.10 30 spaces a1 ball 0.75 0.15 identifier zone 0.10 @ 1.27 = 38.10 corner
130 lucent technologies inc. preliminary data sheet august 2000 orca series 4 fpgas package outline drawings (continued) 680-pin pbgam dimensions are in millimeters. 5-4406(f) seating plane solder ball 0.50 0.10 0.20 35.00 t d h al f k b p m l j ah r c e y n u an g ad v am aj ag ae ac aa w ap ak af ab a 19 30 26 28 24 32 22 20 18 4 6 8 10121416 2 34 52325 731 29 15 21 327 11 17 913 1 33 33 spaces @ 1.00 = 33.00 33 spaces a1 ball 0.64 0.15 a1 ball @ 1.00 = 33.00 corner 30.00 1.170 + 0.70 C 0.00 35.00 30.00 + 0.70 C 0.00 identifier zone 2.51 max 0.61 0.08
lucent technologies inc. 131 preliminary data sheet august 2000 orca series 4 fpgas ordering information 5-6435 (f) table 47 . series 4 package matrix (speed grades) table 48. package options packages 352-pin pbga 1.27 mm 432-pin ebga 1.27 mm 680-pin pbgam 1 mm OR4E2 -1/-2 -1/-2 or4e4 -1/-2 -1/-2 -1/-2 or4e6 -1/-2 -1/-2 -1/-2 or4e10 -1/-2 symbol description ba plastic ball grid array (pbga) bc enhanced ball grid array (ebga) bm plastic multilayer ball grid array (pbgam) device type package type or4exx -1 bm number of pins 680 speed grade
preliminary data sheet orca series 4 fpgas august 2000 lucent technologies inc. reserves the right to make changes to the product(s) or information contained herein without notice. n o liability is assumed as a result of their use or application. no rights under any patent accompany the sale of any such product(s) or information. orca is a registered trademark of lucent technologies inc. foundry is a trademark of xilinx, inc. copyright ? 2000 lucent technologies inc. all rights reserved august 2000 ds00-221fpga for additional information, contact your microelectronics group account manager or the following: internet: http://www.lucent.com/micro , or for fpga information, http://www.lucent.com/orca e-mail: docmaster@micro.lucent.com n. america: microelectronics group, lucent technologies inc., 555 union boulevard, room 30l-15p-ba, allentown, pa 18109-3286 1-800-372-2447 , fax 610-712-4106 (in canada: 1-800-553-2448 , fax 610-712-4106) asia pacific: microelectronics group, lucent technologies singapore pte. ltd., 77 science park drive, #03-18 cintech iii, singap ore 118256 tel. (65) 778 8833 , fax (65) 777 7495 china: microelectronics group, lucent technologies (china) co., ltd., a-f2, 23/f, zao fong universe building, 1800 zhong shan xi road, shanghai 200233 p. r. china tel. (86) 21 6440 0468 , ext. 325 , fax (86) 21 6440 0652 japan: microelectronics group, lucent technologies japan ltd., 7-18, higashi-gotanda 2-chome, shinagawa-ku, tokyo 141, japan tel. (81) 3 5421 1600 , fax (81) 3 5421 1700 europe: data requests: microelectronics group dataline: tel. (44) 7000 582 368 , fax (44) 1189 328 148 technical inquiries: germany: (49) 89 95086 0 (munich), united kingdom: (44) 1344 865 900 (ascot), france: (33) 1 40 83 68 00 (paris), sweden: (46) 8 594 607 00 (stockholm), finland: (358) 9 4354 2800 (helsinki), italy: (39) 02 6608131 (milan), spain: (34) 1 807 1441 (madrid)

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